Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: drop FSP 1.1 [PATCH 2/2] ......................................................................
soc/intel/skylake: drop FSP 1.1 [PATCH 2/2]
Follow-up commit where only files are moved and paths adapted to make review of the actual fsp drop easier.
Signed-off-by: Michael Niewöhner foss@mniewoehner.de Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973 --- M src/mainboard/intel/kunimitsu/Makefile.inc R src/mainboard/intel/kunimitsu/romstage.c M src/soc/intel/skylake/Makefile.inc R src/soc/intel/skylake/chip.c R src/soc/intel/skylake/include/soc/ramstage.h R src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/romstage/Makefile.inc R src/soc/intel/skylake/romstage/romstage.c 8 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35868/1
diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 826c958..9a667d6 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -29,5 +29,3 @@ ramstage-y += ramstage.c
smm-y += smihandler.c - -romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs)) diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage.c similarity index 100% rename from src/mainboard/intel/kunimitsu/romstage_fsp20.c rename to src/mainboard/intel/kunimitsu/romstage.c diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 8174765..cb0906c 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -42,7 +42,7 @@ romstage-y += uart.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-y += chip_fsp20.c +ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += elog.c ramstage-y += finalize.c @@ -100,7 +100,6 @@
CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include -CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
# Currently used for microcode path. CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip.c similarity index 100% rename from src/soc/intel/skylake/chip_fsp20.c rename to src/soc/intel/skylake/chip.c diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h similarity index 97% rename from src/soc/intel/skylake/include/fsp20/soc/ramstage.h rename to src/soc/intel/skylake/include/soc/ramstage.h index e5660a6..4157c4e 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/soc/ramstage.h @@ -21,7 +21,7 @@ #include <fsp/api.h> #include <fsp/util.h>
-#include "../../../chip.h" +#include "../../chip.h"
#define FSP_SIL_UPD FSP_S_CONFIG #define FSP_MEM_UPD FSP_M_CONFIG diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h similarity index 100% rename from src/soc/intel/skylake/include/fsp20/soc/romstage.h rename to src/soc/intel/skylake/include/soc/romstage.h diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 7bd1c6f..dff89ce 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,3 +1,3 @@ romstage-y += ../../../../cpu/intel/car/romstage.c -romstage-y += romstage_fsp20.c +romstage-y += romstage.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage.c similarity index 100% rename from src/soc/intel/skylake/romstage/romstage_fsp20.c rename to src/soc/intel/skylake/romstage/romstage.c
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: drop FSP 1.1 [PATCH 2/2] ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35868/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35868/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/skylake: drop FSP 1.1 [PATCH 2/2] Maybe:
Rename files after FSP 1.1 to FSP 2.0 switch
Hello Patrick Rudolph, Matt DeVillier, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35868
to look at the new patch set (#2).
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
soc/intel/skylake: move/rename files after drop of FSP 1.1
Follow-up commit where only files are moved and paths adapted to make review of the previous commit easier.
Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/intel/kunimitsu/Makefile.inc R src/mainboard/intel/kunimitsu/romstage.c M src/soc/intel/skylake/Makefile.inc R src/soc/intel/skylake/chip.c R src/soc/intel/skylake/include/soc/ramstage.h R src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/romstage/Makefile.inc R src/soc/intel/skylake/romstage/romstage.c 8 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35868/2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35868/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35868/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/skylake: drop FSP 1.1 [PATCH 2/2]
Maybe: […]
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Uploaded patch set 3: Patch Set 2 was rebased.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Uploaded patch set 4: New patch set was added with same tree, parent, and commit message as Patch Set 3.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Uploaded patch set 5.
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35868
to look at the new patch set (#5).
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
soc/intel/skylake: move/rename files after drop of FSP 1.1
Follow-up commit where only files are moved and paths adapted to make review of the previous commit easier.
Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/intel/kunimitsu/Makefile.inc R src/mainboard/intel/kunimitsu/romstage.c M src/soc/intel/skylake/Makefile.inc R src/soc/intel/skylake/chip.c R src/soc/intel/skylake/include/soc/ramstage.h R src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/romstage/Makefile.inc R src/soc/intel/skylake/romstage/romstage.c 8 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35868/5
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Patch Set 5: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Uploaded patch set 6: Patch Set 5 was rebased.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Uploaded patch set 7: Patch Set 6 was rebased.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Patch Set 7: Code-Review+1
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35868
to look at the new patch set (#8).
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
soc/intel/skylake: move/rename files after drop of FSP 1.1
Follow-up commit where only files are moved and paths adapted to make review of the previous commit easier.
Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/intel/kunimitsu/Makefile.inc R src/mainboard/intel/kunimitsu/romstage.c M src/soc/intel/skylake/Makefile.inc R src/soc/intel/skylake/chip.c R src/soc/intel/skylake/include/soc/ramstage.h R src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/romstage/Makefile.inc R src/soc/intel/skylake/romstage/romstage.c 8 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35868/8
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Patch Set 8: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Uploaded patch set 11: New patch set was added with same tree, parent, and commit message as Patch Set 10.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Patch Set 12: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
Patch Set 12: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35868 )
Change subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 ......................................................................
soc/intel/skylake: move/rename files after drop of FSP 1.1
Follow-up commit where only files are moved and paths adapted to make review of the previous commit easier.
Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Signed-off-by: Matt DeVillier matt.devillier@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35868 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/kunimitsu/Makefile.inc R src/mainboard/intel/kunimitsu/romstage.c M src/soc/intel/skylake/Makefile.inc R src/soc/intel/skylake/chip.c R src/soc/intel/skylake/include/soc/ramstage.h R src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/romstage/Makefile.inc R src/soc/intel/skylake/romstage/romstage.c 8 files changed, 3 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Matt DeVillier: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 826c958..9a667d6 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -29,5 +29,3 @@ ramstage-y += ramstage.c
smm-y += smihandler.c - -romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs)) diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage.c similarity index 100% rename from src/mainboard/intel/kunimitsu/romstage_fsp20.c rename to src/mainboard/intel/kunimitsu/romstage.c diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 8174765..cb0906c 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -42,7 +42,7 @@ romstage-y += uart.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-y += chip_fsp20.c +ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += elog.c ramstage-y += finalize.c @@ -100,7 +100,6 @@
CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include -CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
# Currently used for microcode path. CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip.c similarity index 100% rename from src/soc/intel/skylake/chip_fsp20.c rename to src/soc/intel/skylake/chip.c diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h similarity index 97% rename from src/soc/intel/skylake/include/fsp20/soc/ramstage.h rename to src/soc/intel/skylake/include/soc/ramstage.h index e5660a6..4157c4e 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/soc/ramstage.h @@ -21,7 +21,7 @@ #include <fsp/api.h> #include <fsp/util.h>
-#include "../../../chip.h" +#include "../../chip.h"
#define FSP_SIL_UPD FSP_S_CONFIG #define FSP_MEM_UPD FSP_M_CONFIG diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h similarity index 100% rename from src/soc/intel/skylake/include/fsp20/soc/romstage.h rename to src/soc/intel/skylake/include/soc/romstage.h diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 7bd1c6f..dff89ce 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,3 +1,3 @@ romstage-y += ../../../../cpu/intel/car/romstage.c -romstage-y += romstage_fsp20.c +romstage-y += romstage.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage.c similarity index 100% rename from src/soc/intel/skylake/romstage/romstage_fsp20.c rename to src/soc/intel/skylake/romstage/romstage.c
-
Matt DeVillier (Code Review) -
Michael Niewöhner (Code Review)
-
Nico Huber (Code Review)
-
Paul Menzel (Code Review)