Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69669 )
Change subject: sb/intel/common: Fix GPE0 related register conflict ......................................................................
sb/intel/common: Fix GPE0 related register conflict
When ACPI GPE0 block was extended to 64 events or 8 bytes, ACPI PM register space was slightly modified. After adjustment, PM2_CNT register moved to 0x50 where register SS_CNT was previously defined to be.
For platforms that have a valid use for PM2_CNT==0x50 in their FADT, remove overlapping definition of SS_CNT.
On i82801dx/gx ACPI GPE0 supports 32 events, reset_gpe0_status() incorrectly addressed also GPE0_EN register. For a bit cleaner implementation, define GPE0_HAS_64_EVENTS.
Change-Id: Iec83e9010146ebd487a61f542ac5c6f4c6a60833 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/pch.h 6 files changed, 51 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/69669/1
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 34b36c3..2ebec62 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -428,7 +428,6 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -462,8 +461,9 @@ #define ALT_GP_SMI_STS 0x3a #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 -#define SS_CNT 0x50 +#define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 + #define TCO1_STS 0x64 #define TCO1_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index a43b95c..8ecb74c 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -73,6 +73,7 @@ { printk(BIOS_DEBUG, "SMI_STS: "); if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); @@ -100,13 +101,15 @@ */ u64 reset_gpe0_status(void) { - u32 reg_h, reg_l; + u32 reg_h = 0, reg_l;
reg_l = read_pmbase32(GPE0_STS); - reg_h = read_pmbase32(GPE0_STS + 4); + if (GPE0_HAS_64_EVENTS) + reg_h = read_pmbase32(GPE0_STS + 4); /* set status bits are cleared by writing 1 to them */ write_pmbase32(GPE0_STS, reg_l); - write_pmbase32(GPE0_STS + 4, reg_h); + if (GPE0_HAS_64_EVENTS) + write_pmbase32(GPE0_STS + 4, reg_h);
return (((u64)reg_h) << 32) | reg_l; } @@ -128,7 +131,7 @@ if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "USB5 "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97/USB5 "); if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index ff7b5e8..5cf76b6 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -5,6 +5,9 @@
#include <cpu/x86/smm.h>
+#define GPE0_HAS_64_EVENTS \ + (!(CONFIG(SOUTHBRIDGE_INTEL_I82801DX) || CONFIG(SOUTHBRIDGE_INTEL_I82801GX))) + #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 #define SMI_LOCK (1 << 4) @@ -54,13 +57,18 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) + +#if GPE0_HAS_64_EVENTS +#define GPE0_STS 0x20 +#define GPE0_EN 0x28 // GPE0_STS + 8 +#define PM2_CNT 0x50 // mobile only +#else #define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 -#else -#define PM2_CNT 0x50 // mobile only -#define GPE0_STS 0x20 -#endif /* CONFIG(SOUTHBRIDGE_INTEL_I82801GX) */ +#define GPE0_EN 0x2c // GPE0_STS + 4 +#endif + +/* def GPE0_STS */ #define USB4_STS (1 << 14) /* i82801gx only */ #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -71,11 +79,8 @@ #define TCOSCI_STS (1 << 6) #define SWGPE_STS (1 << 2) #define HOT_PLUG_STS (1 << 1) -#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) -#define GPE0_EN 0x2c -#else -#define GPE0_EN 0x28 -#endif /* CONFIG(SOUTHBRIDGE_INTEL_I82801GX) */ + +/* def GPE0_EN */ #define PME_B0_EN (1 << 13) #define PME_EN (1 << 11) #define TCOSCI_EN (1 << 6) @@ -98,8 +103,7 @@ #define ALT_GP_SMI_STS 0x3a #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 -#define SS_CNT 0x50 -#define C3_RES 0x54 + #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define BOOT_STS (1 << 18) diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index c07e581..7946bd5 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -113,9 +113,6 @@ #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 -#define LV3 0x15 -#define LV4 0x16 -#define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 #define PME_B0_STS (1 << 13) #define USB3_STS (1 << 12) @@ -155,7 +152,6 @@ #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 #define SS_CNT 0x50 -#define C3_RES 0x54
#define TCOBASE 0x60 /* TCO Base Address Register */ #define TCO1_CNT 0x08 /* TCO1 Control Register */ diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 1f5b4ea..c42fe0f 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -409,7 +409,6 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -443,8 +442,9 @@ #define ALT_GP_SMI_STS 0x3a #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 -#define SS_CNT 0x50 +#define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 + #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 1623274..dcd3ce5 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -581,7 +581,6 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -617,8 +616,9 @@ #define ALT_GP_SMI_STS 0x3a #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 -#define SS_CNT 0x50 +#define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 + #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66
-
Kyösti Mälkki (Code Review)