Change in coreboot[master]: mb/razer/blade_stealth_kbl: Relocate devicetree FSP settings
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43891 )
Change subject: mb/razer/blade_stealth_kbl: Relocate devicetree FSP settings ......................................................................
mb/razer/blade_stealth_kbl: Relocate devicetree FSP settings
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: Ibce057b5bcaf90697c7bdd5731948c1ea4e4ef7d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 1 file changed, 49 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/43891/1
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index dc7c42b..b3dd150 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -27,27 +27,12 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "SataPortsEnable[1]" = "0" - register "SataPortsEnable[2]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -131,17 +116,6 @@ .dc_loadline = 310, }"
- # Enable Root Ports 3, 5 and 9 - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - - register "PcieRpLtrEnable[2]" = "1" - register "PcieRpLtrEnable[4]" = "1" - register "PcieRpLtrEnable[8]" = "1" - - register "PcieRpHotPlug[4]" = "1" - # USB register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) @@ -195,7 +169,11 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # Thermal Subsystem + device pci 04.0 off # Thermal Subsystem + + # FIXME: Does not correspond with devicetree settings + register "Device4Enable" = "1" + end device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) @@ -213,28 +191,55 @@ end # I2C Controller #1 device pci 15.2 off end # I2C Controller #2 device pci 15.3 off end # I2C Controller #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA + device pci 17.0 off # SATA + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "0" + end device pci 19.0 on end # I2C Controller #4 device pci 19.1 off end # I2C Controller #5 device pci 19.2 off end # UART #2 device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.2 off # PCI Express Port 3 + + # FIXME: This RP is disabled? + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + end device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.4 on # PCI Express Port 5 + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1e.0 on end # Serial IO UART0 + + # eMMC/SD disabled + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + device pci 1f.0 on # LPC chip drivers/pc80/tpm device pnp 0c31.0 on end @@ -256,13 +261,21 @@ device pnp 6e.17 off end device pnp 6e.18 off end device pnp 6e.19 off end - end #superio/ite/it8528e + end # superio/ite/it8528e end # LPC Bridge device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.3 on # Intel HDA + register "EnableAzalia" = "1" + end + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 off # GbE + register "EnableLan" = "0" + end + + register "EnableTraceHub" = "0" end end
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43891 )
Change subject: mb/razer/blade_stealth_kbl: Relocate devicetree FSP settings ......................................................................
Patch Set 1: Code-Review+2
Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43891
to look at the new patch set (#2).
Change subject: mb/razer/blade_stealth_kbl: Relocate devicetree settings ......................................................................
mb/razer/blade_stealth_kbl: Relocate devicetree settings
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: Ibce057b5bcaf90697c7bdd5731948c1ea4e4ef7d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 1 file changed, 49 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/43891/2
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43891 )
Change subject: mb/razer/blade_stealth_kbl: Relocate devicetree settings ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Felix Singer (Code Review)