[S] Change in coreboot[master]: soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72735 )

Change subject: soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges
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soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges

Commit b171f768127d ("soc/amd/*: Hook up GPP bridges ops to devicetree")
missed adding the amd_external_pcie_gpp_ops ops to the gpp_gfx_bridge
PCIe ports, so add them. Those devices were previously covered by the
PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 PCI device ID in the list that
got removed in the referenced commit.

Signed-off-by: Felix Held 
Change-Id: I55434bf486569b32901b3840193a09cc5955abb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72735
Tested-by: build bot (Jenkins) 
Reviewed-by: Fred Reitberger 
---
M src/soc/amd/cezanne/chipset.cb
1 file changed, 22 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Fred Reitberger: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb
index 691153f..c779390 100644
--- a/src/soc/amd/cezanne/chipset.cb
+++ b/src/soc/amd/cezanne/chipset.cb
@@ -8,9 +8,9 @@
    	device pci 00.2 alias iommu off ops amd_iommu_ops end

device pci 01.0 on end # Dummy Host Bridge, do not disable
-		device pci 01.1 alias gpp_gfx_bridge_0 off end
-		device pci 01.2 alias gpp_gfx_bridge_1 off end
-		device pci 01.3 alias gpp_gfx_bridge_2 off end
+		device pci 01.1 alias gpp_gfx_bridge_0 off ops amd_external_pcie_gpp_ops end
+		device pci 01.2 alias gpp_gfx_bridge_1 off ops amd_external_pcie_gpp_ops end
+		device pci 01.3 alias gpp_gfx_bridge_2 off ops amd_external_pcie_gpp_ops end

device pci 02.0 on end # Dummy Host Bridge, do not disable
    	device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end