Change in coreboot[master]: soc/intel/alderlake: Add option to make MRC log silent

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60441 )

Change subject: soc/intel/alderlake: Add option to make MRC log silent
......................................................................

soc/intel/alderlake: Add option to make MRC log silent

Typically, FSP-M aka MRC debug log level is default set to `3`
meaning prints all `Load, Error, Warnings & Info` Messages.

Sometime it's too much information to parse even when users
aren't required to have such detailed information hence,
added option to make the MRC serial debug message
silent when user selects `SILENT_FSP_M_DEBUG_MESSAGE` config.

TEST=FSP-M debug log suggested default `SerialDebugMrcLevel`
UPD value is `3`. While user selects `SILENT_FSP_M_DEBUG_MESSAGE`
config `SerialDebugMrcLevel` UPD value is overridden to '0'
aka disable.

Signed-off-by: Subrata Banik 
Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718
---
M src/drivers/intel/fsp2_0/Kconfig.debug_blob
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/fsp_params.c
3 files changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/60441/1

diff --git a/src/drivers/intel/fsp2_0/Kconfig.debug_blob b/src/drivers/intel/fsp2_0/Kconfig.debug_blob
index e9e6053..9c814dd 100644
--- a/src/drivers/intel/fsp2_0/Kconfig.debug_blob
+++ b/src/drivers/intel/fsp2_0/Kconfig.debug_blob
@@ -62,4 +62,12 @@
      requires platform support to snapshot and verify that config
      matches snapshot.

+config SILENT_FSP_M_DEBUG_MESSAGE
+	bool
+	default n
+	help
+	  Select this option for silent or quite FSP-M boot even with debug
+	  enable FSP-M binary. This feature is helpful to reduce the boot time
+	  latency with debug FSP binaries.
+
 endif # PLATFORM_USES_FSP2_0
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 5419783..335a4f9 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -320,6 +320,21 @@
      0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power),
      7:Manual

+config SOC_INTEL_ALDERLAKE_MRC_DEBUG_CONSENT
+	int "Debug Consent for FSP-M"
+	# MRC Serial Debug Message Level `Load, Error, Warnings & Info`
+	# is useful for developers so set the default to `3`.
+	# If SILENT_FSP_M_DEBUG_MESSAGE=y then make FSP-M silent/disable.
+	default 0 if SILENT_FSP_M_DEBUG_MESSAGE
+	default 3
+	help
+	  This is to control MRC serial debug interface for FSP-M.
+
+	  Desired MRC serial debug level are
+	  0:Disable, 1:Error Only, 2:Error & Warnings,
+	  3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event,
+	  5:Load, Error, Warnings, Info & Verbose.
+
 config DATA_BUS_WIDTH
    int
    default 128
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 8959bf7..be266d9 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -312,6 +312,9 @@
 static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg,
    	const struct soc_intel_alderlake_config *config)
 {
+	/* Set MRC debug level */
+	m_cfg->SerialDebugMrcLevel = CONFIG_SOC_INTEL_ALDERLAKE_MRC_DEBUG_CONSENT;
+
    /* Set debug probe type */
    m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;