[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve PRMRR

[Arthur Heymans (Code Review)]

Attention is currently required from: Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Arthur Heymans has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84314?usp=email )

Change subject: soc/intel/xeon_sp: Reserve PRMRR
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Patch Set 1:

(4 comments)

File src/cpu/x86/mtrr/mtrr.c:

https://review.coreboot.org/c/coreboot/+/84314/comment/7bc17768_0723e2c3?usp... :
PS1, Line 115: static inline uint64_t range_entry_base_mtrr_addr(struct range_entry *r)
             : {
             : 	return PHYS_TO_RANGE_ADDR(range_entry_base(r));
             : }
             : 
             : static inline uint64_t range_entry_end_mtrr_addr(struct range_entry *r)
             : {
             : 	return PHYS_TO_RANGE_ADDR(range_entry_end(r));
             : }
I suppose this could be exposed intead of a new function?

File src/include/cpu/x86/mtrr.h:

https://review.coreboot.org/c/coreboot/+/84314/comment/a088a6e4_af7a4d2f?usp... :
PS1, Line 130: uint64_t calculate_var_mtrr_size(uint64_t mask);
use a static inline.

File src/soc/intel/xeon_sp/uncore.c:

https://review.coreboot.org/c/coreboot/+/84314/comment/3ff17cb5_9c038de9?usp... :
PS1, Line 176: msr.hi << 32 | msr.lo;
there is msr.raw now to avoid this.

https://review.coreboot.org/c/coreboot/+/84314/comment/f0ac4867_e0b5e9bb?usp... :
PS1, Line 340: get_prmrr_count
do you know that all generations support 7 of these registers, which the weak function suggests? if not exception will be thrown.