Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46923 )
Change subject: cpu/intel/haswell/acpi.c: Use C-state enum definitions ......................................................................
cpu/intel/haswell/acpi.c: Use C-state enum definitions
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I0ca98cbe45e10d233607f68923f08752fdda9698 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 3 files changed, 27 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/46923/1
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index d257d86..7c99df3 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -15,15 +15,15 @@ #include <southbridge/intel/lynxpoint/pch.h>
static int cstate_set_lp[3] = { - 2, - 3, - 9, + C_STATE_C1E, + C_STATE_C3, + C_STATE_C7S_LONG_LAT, };
static int cstate_set_trad[3] = { - 1, - 3, - 5, + C_STATE_C1, + C_STATE_C3, + C_STATE_C6_LONG_LAT, };
static int get_cores_per_package(void) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index d02cba6..e45acd5 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -140,6 +140,27 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif
+/* + * List of supported C-states for Haswell and Broadwell. + * Only the ULT parts support C8, C9, and C10. + */ +enum { + C_STATE_C0 = 0, + C_STATE_C1 = 1, + C_STATE_C1E = 2, + C_STATE_C3 = 3, + C_STATE_C6_SHORT_LAT = 4, + C_STATE_C6_LONG_LAT = 5, + C_STATE_C7_SHORT_LAT = 6, + C_STATE_C7_LONG_LAT = 7, + C_STATE_C7S_SHORT_LAT = 8, + C_STATE_C7S_LONG_LAT = 9, + C_STATE_C8 = 10, + C_STATE_C9 = 11, + C_STATE_C10 = 12, + NUM_C_STATES, +}; + /* Lock MSRs */ void intel_cpu_haswell_finalize_smm(void);
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 1920350..04f5802 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -20,27 +20,6 @@ #include "haswell.h" #include "chip.h"
-/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46923 )
Change subject: cpu/intel/haswell/acpi.c: Use C-state enum definitions ......................................................................
Patch Set 3: Code-Review+1
Hello build bot (Jenkins), Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46923
to look at the new patch set (#6).
Change subject: cpu/intel/haswell/acpi.c: Use C-state enum definitions ......................................................................
cpu/intel/haswell/acpi.c: Use C-state enum definitions
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I0ca98cbe45e10d233607f68923f08752fdda9698 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 3 files changed, 27 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/46923/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46923 )
Change subject: cpu/intel/haswell/acpi.c: Use C-state enum definitions ......................................................................
Patch Set 15:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/46923/comment/43d19c34_91feb7f8 PS15, Line 9: Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. I think I tested some Haswell-LP board as well, but I don't remember which.
Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46923 )
Change subject: cpu/intel/haswell/acpi.c: Use C-state enum definitions ......................................................................
Patch Set 15: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46923 )
Change subject: cpu/intel/haswell/acpi.c: Use C-state enum definitions ......................................................................
cpu/intel/haswell/acpi.c: Use C-state enum definitions
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I0ca98cbe45e10d233607f68923f08752fdda9698 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46923 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 3 files changed, 27 insertions(+), 27 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index d257d86..7c99df3 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -15,15 +15,15 @@ #include <southbridge/intel/lynxpoint/pch.h>
static int cstate_set_lp[3] = { - 2, - 3, - 9, + C_STATE_C1E, + C_STATE_C3, + C_STATE_C7S_LONG_LAT, };
static int cstate_set_trad[3] = { - 1, - 3, - 5, + C_STATE_C1, + C_STATE_C3, + C_STATE_C6_LONG_LAT, };
static int get_cores_per_package(void) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 284ff01..5084cd3 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -125,6 +125,27 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif
+/* + * List of supported C-states for Haswell and Broadwell. + * Only the ULT parts support C8, C9, and C10. + */ +enum { + C_STATE_C0 = 0, + C_STATE_C1 = 1, + C_STATE_C1E = 2, + C_STATE_C3 = 3, + C_STATE_C6_SHORT_LAT = 4, + C_STATE_C6_LONG_LAT = 5, + C_STATE_C7_SHORT_LAT = 6, + C_STATE_C7_LONG_LAT = 7, + C_STATE_C7S_SHORT_LAT = 8, + C_STATE_C7S_LONG_LAT = 9, + C_STATE_C8 = 10, + C_STATE_C9 = 11, + C_STATE_C10 = 12, + NUM_C_STATES, +}; + /* Lock MSRs */ void intel_cpu_haswell_finalize_smm(void);
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index dd1970c..fa2f3f6 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -20,27 +20,6 @@ #include "haswell.h" #include "chip.h"
-/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Michael Niewöhner (Code Review)
-
Patrick Georgi (Code Review)