Attention is currently required from: Tarun Tuli, Eran Mitrani, Subrata Banik.
Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71114 )
Change subject: soc/intel/mtl: Add missing claimed memory regions ......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71114/comment/c2e38f49_f7614a65 PS3, Line 13: Please add more details, e.g.
'cbmem -c' snippet: ``` DOMAIN: 0000 read_resources bus 0 link: 0 SA MMIO resource: PCIEXBAR -> base = 0xc0000000, size = 0x10000000 dev: PCI: 00:00.0, index: 0x0, base: 0xc0000000, size: 0x10000000 SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x00020000 dev: PCI: 00:00.0, index: 0x1, base: 0xfedc0000, size: 0x20000 SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x00001000 dev: PCI: 00:00.0, index: 0x2, base: 0xfeda0000, size: 0x1000 SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x00001000 dev: PCI: 00:00.0, index: 0x3, base: 0xfeda1000, size: 0x1000 SA MMIO resource: REGBAR -> base = 0xd0000000, size = 0x10000000 dev: PCI: 00:00.0, index: 0x4, base: 0xd0000000, size: 0x10000000 SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000 dev: PCI: 00:00.0, index: 0x5, base: 0xfed80000, size: 0x4000 SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x00080000 dev: PCI: 00:00.0, index: 0x6, base: 0xfeb00000, size: 0x80000 SA MMIO resource: TPM -> base = 0xfed40000, size = 0x00010000 dev: PCI: 00:00.0, index: 0x7, base: 0xfed40000, size: 0x10000 SA MMIO resource: LT_SECURITY -> base = 0xfed50000, size = 0x00020000 dev: PCI: 00:00.0, index: 0x8, base: 0xfed50000, size: 0x20000 SA MMIO resource: APIC -> base = 0xfec00000, size = 0x00100000 dev: PCI: 00:00.0, index: 0x9, base: 0xfec00000, size: 0x100000 SA MMIO resource: PCH_RESERVED -> base = 0xfd800000, size = 0x01000000 dev: PCI: 00:00.0, index: 0xa, base: 0xfd800000, size: 0x1000000 SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000 dev: PCI: 00:00.0, index: 0xb, base: 0xc0000000, size: 0x10000000 SA MMIO resource: DSM -> base = 0x7c000000, size = 0x04000000 dev: PCI: 00:00.0, index: 0xc, base: 0x7c000000, size: 0x4000000 SA MMIO resource: TSEG -> base = 0x7b000000, size = 0x00800000 dev: PCI: 00:00.0, index: 0xd, base: 0x7b000000, size: 0x800000 SA MMIO resource: GSM -> base = 0x7b800000, size = 0x00800000 dev: PCI: 00:00.0, index: 0xe, base: 0x7b800000, size: 0x800000 dev: PCI: 00:00.0, index: 0xf, base: 0x0, size: 0xa0000 dev: PCI: 00:00.0, index: 0x10, base: 0xc0000, size: 0x75f40000 dev: PCI: 00:00.0, index: 0x11, base: 0x76000000, size: 0xa000000 Available memory above 4GB: 6144M dev: PCI: 00:00.0, index: 0x12, base: 0x100000000, size: 0x180000000 dev: PCI: 00:00.0, index: 0x13, base: 0xa0000, size: 0x20000 dev: PCI: 00:00.0, index: 0x14, base: 0xc0000, size: 0x40000 ```
'dmesg' snippet: ``` BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] reserved BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x00000000759a9fff] usable BIOS-e820: [mem 0x00000000759aa000-0x000000007fffffff] reserved BIOS-e820: [mem 0x00000000c0000000-0x00000000e0ffffff] reserved BIOS-e820: [mem 0x00000000f8000000-0x00000000f9ffffff] reserved BIOS-e820: [mem 0x00000000fd800000-0x00000000fe7fffff] reserved BIOS-e820: [mem 0x00000000feb00000-0x00000000feb7ffff] reserved BIOS-e820: [mem 0x00000000fec00000-0x00000000fecfffff] reserved BIOS-e820: [mem 0x00000000fed40000-0x00000000fed6ffff] reserved BIOS-e820: [mem 0x00000000fed80000-0x00000000fed83fff] reserved BIOS-e820: [mem 0x00000000feda0000-0x00000000feda1fff] reserved BIOS-e820: [mem 0x00000000fedc0000-0x00000000feddffff] reserved BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved BIOS-e820: [mem 0x0000000100000000-0x000000027fffffff] usable BIOS-e820: [mem 0x000003fff0aa0000-0x000003fff0aa1fff] reserved ```
File src/soc/intel/meteorlake/include/soc/systemagent.h:
https://review.coreboot.org/c/coreboot/+/71114/comment/52570d94_68d2d1a4 PS3, Line 49: 0xFED50000 As per MTL FAS, There are 2 ranges for LT: FED20000-FED7FFFF FED50000-FED6FFFF
File src/soc/intel/meteorlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/71114/comment/3d4f25e4_dedf87a9 PS3, Line 27: { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, : "PCIEXBAR" }, : { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, : { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, : { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, : { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, : { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, : : /* first field (sa_mmio_descriptor.index) is not used, setting to 0: */ : { 0, CRAB_ABORT_BASE_ADDR, CRAB_ABORT_SIZE, "CRAB_ABORT" }, : { 0, TPM_BASE_ADDRESS, TPM_SIZE, "TPM" }, : { 0, LT_SECURITY_BASE_ADDR, LT_SECURITY_SIZE, "LT_SECURITY" }, : { 0, IO_APIC_ADDR, APIC_SIZE, "APIC" }, : // PCH_PRESERVERD covers: : // TraceHub SW BAR, SBREG, PMC MBAR, SPI BAR0, SerialIo BAR in ACPI mode : // eSPI LGMR BAR, eSPI2 SEGMR BAR, TraceHub MTB BAR, TraceHub FW BAR : // see fsp/ClientOneSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h : { 0, PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE, "PCH_RESERVED" }, Have you already checked these ranges against MTL FAS sec5.5?
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Kapil Porwal (Code Review)