Change in coreboot[master]: nb/amd/agesa: define DDR3_SPD_SIZE as a common value

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Mike Banon (Code Review)

15 Aug 2020 15 Aug '20

9:45 a.m.

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

nb/amd/agesa: define DDR3_SPD_SIZE as a common value

Move a size of DDR3 SPD memory (always 256 bytes) to a common define.

Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 --- M src/northbridge/amd/agesa/dimmSpd.h M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c 4 files changed, 5 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44498/1

diff --git a/src/northbridge/amd/agesa/dimmSpd.h b/src/northbridge/amd/agesa/dimmSpd.h index dbcb106..c627bb4 100644 --- a/src/northbridge/amd/agesa/dimmSpd.h +++ b/src/northbridge/amd/agesa/dimmSpd.h @@ -3,6 +3,8 @@ #ifndef _DIMMSPD_H_ #define _DIMMSPD_H_

+#define DDR3_SPD_SIZE 256 + AGESA_STATUS AmdMemoryReadSPD (IN UINT32 Func, IN UINTN Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);

diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index e4d1eab..3ce84a4 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -40,7 +40,7 @@ if (spdAddress == 0) return AGESA_ERROR;

- int err = smbus_readSpd(spdAddress, (void *) info->Buffer, 256); + int err = smbus_readSpd(spdAddress, (void *) info->Buffer, DDR3_SPD_SIZE); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c index 6504d14..70a7b92 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c @@ -39,7 +39,7 @@ if (spdAddress == 0) return AGESA_ERROR;

- int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 256); + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, DDR3_SPD_SIZE); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c index b20216f..58b35e0 100644 --- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -39,7 +39,7 @@ if (spdAddress == 0) return AGESA_ERROR;

- int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 256); + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, DDR3_SPD_SIZE); if (err) return AGESA_ERROR; return AGESA_SUCCESS;

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Mike Banon (Code Review)

15 Aug 15 Aug

10:03 a.m.

Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

Patch Set 1:

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/44498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Gerrit-Change-Number: 44498 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon mikebdp2@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Sat, 15 Aug 2020 08:03:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Angel Pons (Code Review)

3:01 p.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG@9 PS1, Line 9: Move a size of DDR3 SPD memory (always 256 bytes) to a common define. I think there's more instances of `256` elsewhere?

-- To view, visit https://review.coreboot.org/c/coreboot/+/44498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Gerrit-Change-Number: 44498 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon mikebdp2@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Sat, 15 Aug 2020 13:01:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Mike Banon (Code Review)

16 Aug 16 Aug

8:07 p.m.

Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG@9 PS1, Line 9: Move a size of DDR3 SPD memory (always 256 bytes) to a common define.

...

I think there's more instances of `256` elsewhere?

Other instances of `256` are outside nb/amd/agesa, i.e.: ./src/vendorcode/amd/agesa/f16kb/AGESA.h:1612: IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM ./src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttoptsrc.c:150: UINT8 TestBuffer[256]; (similar for f14/f15tn) and maybe some other things I've missed.

Do you think I should introduce DDR3_SPD_SIZE to these vendorcode places as well?

-- To view, visit https://review.coreboot.org/c/coreboot/+/44498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Gerrit-Change-Number: 44498 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon mikebdp2@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Sun, 16 Aug 2020 18:07:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Angel Pons (Code Review)

9:40 p.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG@9 PS1, Line 9: Move a size of DDR3 SPD memory (always 256 bytes) to a common define.

...

Other instances of `256` are outside nb/amd/agesa, i.e.: […]

If there's a decent enough AGESA header where you could add this definition, I'd add it in vendorcode. If that's too complex, you can always add it as a Kconfig symbol.

-- To view, visit https://review.coreboot.org/c/coreboot/+/44498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Gerrit-Change-Number: 44498 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon mikebdp2@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Sun, 16 Aug 2020 19:40:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Comment-In-Reply-To: Mike Banon mikebdp2@gmail.com Gerrit-MessageType: comment

Mike Banon (Code Review)

17 Aug 17 Aug

3:42 p.m.

Hello build bot (Jenkins), Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44498

to look at the new patch set (#2).

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

nb/amd/agesa: define DDR3_SPD_SIZE as a common value

Move a size of DDR3 SPD memory (always 256 bytes) to a common define.

Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 --- M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/vendorcode/amd/agesa/f14/AGESA.h M src/vendorcode/amd/agesa/f15tn/AGESA.h M src/vendorcode/amd/agesa/f16kb/AGESA.h 6 files changed, 9 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44498/2

-- To view, visit https://review.coreboot.org/c/coreboot/+/44498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Gerrit-Change-Number: 44498 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon mikebdp2@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Mike Banon (Code Review)

4:06 p.m.

Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG@9 PS1, Line 9: Move a size of DDR3 SPD memory (always 256 bytes) to a common define.

...

If there's a decent enough AGESA header where you could add this definition, I'd add it in vendorcod […]

Done.

-- To view, visit https://review.coreboot.org/c/coreboot/+/44498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Gerrit-Change-Number: 44498 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon mikebdp2@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Mon, 17 Aug 2020 14:06:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Comment-In-Reply-To: Mike Banon mikebdp2@gmail.com Gerrit-MessageType: comment

Angel Pons (Code Review)

18 Aug 18 Aug

3:38 p.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG@9 PS1, Line 9: Move a size of DDR3 SPD memory (always 256 bytes) to a common define.

...

Done.

Um, but replace the other instances of `256` as well?

-- To view, visit https://review.coreboot.org/c/coreboot/+/44498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Gerrit-Change-Number: 44498 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon mikebdp2@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 18 Aug 2020 13:38:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Comment-In-Reply-To: Mike Banon mikebdp2@gmail.com Gerrit-MessageType: comment

Mike Banon (Code Review)

9:26 p.m.

Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG@9 PS1, Line 9: Move a size of DDR3 SPD memory (always 256 bytes) to a common define.

...

Um, but replace the other instances of `256` as well?

Sadly it's really not obvious (at least to me) which of these references are guaranteed to stand for SPD size. I replaced only one for which I'm 100% confident, to be on the safe side.

-- To view, visit https://review.coreboot.org/c/coreboot/+/44498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Gerrit-Change-Number: 44498 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon mikebdp2@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 18 Aug 2020 19:26:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Comment-In-Reply-To: Mike Banon mikebdp2@gmail.com Gerrit-MessageType: comment

Angel Pons (Code Review)

20 Aug 20 Aug

10:16 a.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

Patch Set 2: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG@9 PS1, Line 9: Move a size of DDR3 SPD memory (always 256 bytes) to a common define.

...

Sadly it's really not obvious (at least to me) which of these references are guaranteed to stand for […]

Well, that's what reviews are for 😉

We can handle the rest in a follow-up.

-- To view, visit https://review.coreboot.org/c/coreboot/+/44498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Gerrit-Change-Number: 44498 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon mikebdp2@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Thu, 20 Aug 2020 08:16:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Comment-In-Reply-To: Mike Banon mikebdp2@gmail.com Gerrit-MessageType: comment

Patrick Georgi (Code Review)

24 Aug 24 Aug

11:18 a.m.

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

nb/amd/agesa: define DDR3_SPD_SIZE as a common value

Move a size of DDR3 SPD memory (always 256 bytes) to a common define.

Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44498 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/vendorcode/amd/agesa/f14/AGESA.h M src/vendorcode/amd/agesa/f15tn/AGESA.h M src/vendorcode/amd/agesa/f16kb/AGESA.h 6 files changed, 9 insertions(+), 6 deletions(-)

Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved

- int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 256); + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, DDR3_SPD_SIZE); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c index b20216f..58b35e0 100644 --- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -39,7 +39,7 @@ if (spdAddress == 0) return AGESA_ERROR;

- int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 256); + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, DDR3_SPD_SIZE); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 03f1670..e7d02fa 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -1158,9 +1158,10 @@ /// /// SPD Data for each DIMM. /// +#define DDR3_SPD_SIZE 256 typedef struct _SPD_DEF_STRUCT { IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid - IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM + IN UINT8 Data[DDR3_SPD_SIZE]; ///< Buffer for 256 Bytes of SPD data from DIMM } SPD_DEF_STRUCT;

/// diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h index 922a8ee..d41a5ee 100644 --- a/src/vendorcode/amd/agesa/f15tn/AGESA.h +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -1546,9 +1546,10 @@ /// /// SPD Data for each DIMM. /// +#define DDR3_SPD_SIZE 256 typedef struct _SPD_DEF_STRUCT { IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid - IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM + IN UINT8 Data[DDR3_SPD_SIZE]; ///< Buffer for 256 Bytes of SPD data from DIMM } SPD_DEF_STRUCT;

/// diff --git a/src/vendorcode/amd/agesa/f16kb/AGESA.h b/src/vendorcode/amd/agesa/f16kb/AGESA.h index 7e43de4..853fdc9 100644 --- a/src/vendorcode/amd/agesa/f16kb/AGESA.h +++ b/src/vendorcode/amd/agesa/f16kb/AGESA.h @@ -1621,9 +1621,10 @@ /// /// SPD Data for each DIMM. /// +#define DDR3_SPD_SIZE 256 typedef struct _SPD_DEF_STRUCT { IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid - IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM + IN UINT8 Data[DDR3_SPD_SIZE]; ///< Buffer for 256 Bytes of SPD data from DIMM } SPD_DEF_STRUCT;

///

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9elements QA (Code Review)

7:55 p.m.

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value ......................................................................

Patch Set 3:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/3/7 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/16392 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/16391 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/16390 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/16389 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/16388 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : FAIL : https://lava.9esec.io/r/16394 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/16393

Please note: This test is under development and might not be accurate at all!

-- To view, visit https://review.coreboot.org/c/coreboot/+/44498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Gerrit-Change-Number: 44498 Gerrit-PatchSet: 3 Gerrit-Owner: Mike Banon mikebdp2@gmail.com Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: 9elements QA hardwaretestrobot@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Mon, 24 Aug 2020 17:55:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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9elements QA (Code Review)
Angel Pons (Code Review)
Mike Banon (Code Review)
Patrick Georgi (Code Review)