New patch to review for coreboot: nb/amd/mct_ddr3: Stop receiver enable cycle training after window found

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14544

-gerrit

commit 96b0d7c2fcc9c715877a2f1ff6e0bec03c042f4e
Author: Timothy Pearson 
Date:   Fri Apr 29 01:38:58 2016 -0500

nb/amd/mct_ddr3: Stop receiver enable cycle training after window found

During receiver enable cycle training on Family 15h the entire range
    of possible delays is searched, even though the single passing window
    is often found nearly immediately.  Skip the remainder of the delay
    range after the passing window has been located.

Change-Id: If98217fa8e7de77366762d3c7bb01049a1dc080f
    Signed-off-by: Timothy Pearson 
---
 src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 7ef2900..69a5fe3 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -1617,6 +1617,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
    uint32_t rx_en_offset;
    uint8_t internal_lane;
    uint8_t dct_training_success;
+	uint8_t lane_success_count;
    uint16_t initial_phy_phase_delay[MAX_BYTE_LANES];
    uint16_t current_phy_phase_delay[MAX_BYTE_LANES];
    uint16_t current_read_dqs_delay[MAX_BYTE_LANES];
@@ -1695,6 +1696,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
    		for (lane = 0; lane < lane_count; lane++) {
    			/* Initialize variables */
    			memset(dqs_results_array, 0, sizeof(dqs_results_array));
+				lane_success_count = 0;

/* 2.10.5.8.3 (1) */
    			dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8));
@@ -1721,6 +1723,13 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,

/* 2.10.5.8.3 (4 B) */
    				dqs_results_array[current_phy_phase_delay[lane]] = TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane, lane + 1);
+
+					if (dqs_results_array[current_phy_phase_delay[lane]])
+						lane_success_count++;
+
+					/* Don't bother testing larger values if the end of the passing window was already found */
+					if (!dqs_results_array[current_phy_phase_delay[lane]] && (lane_success_count > 1))
+						break;
    			}

uint16_t phase_delay;