Change in coreboot[master]: Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"

[Paul Fagerburg (Code Review)]

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59149 )

Change subject: Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"
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Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"

This reverts commit ba6fdc892d62741e456ac5628fcd6f869c4cb9af.

Reason for revert: Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1), GPP_R6 ~ GPP_R7 should be NF3 for dmic.

Signed-off-by: David Wu 
Change-Id: I460fd99b4ad4b9c470f692032ff7ea2b51cad388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59149
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
index ba4bbf8..ffdc285 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
@@ -318,9 +318,9 @@
    /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
    PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
    /* R6 : I2S2_TXD ==> DMIC_CLK1_R */
-	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
    /* R7 : I2S2_RXD ==> DMIC_DATA1_R */
-	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),

/* S0 : SNDW0_CLK ==> NC */
    PAD_NC(GPP_S0, NONE),