Change in coreboot[master]: soc/amd/common/blocks/lpc: Explicitly disable serial IRQ

[Martin Roth (Code Review)]

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51077 )

Change subject: soc/amd/common/blocks/lpc: Explicitly disable serial IRQ
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soc/amd/common/blocks/lpc: Explicitly disable serial IRQ

The serirq enable bit defaults to true, so if we want it disabled, we
need to explicitly disable it.

BUG=b:180631748
TEST=Boot majolica and see spurious IRQ 9 gone.

Signed-off-by: Raul E Rangel 
Change-Id: I7f1e18f836f29cb75334dd88c91ad047f5bdfb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51077
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/common/block/lpc/lpc.c
1 file changed, 4 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, but someone else must approve
  Marshall Dawson: Looks good to me, approved

diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 1d019a3..2586ba9 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -28,7 +28,9 @@
    u8 byte;

/* Set up SERIRQ, enable continuous mode */
-	byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE);
+	byte = PM_SERIRQ_NUM_BITS_21;
+	if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
+		byte |= PM_SERIRQ_ENABLE;
    if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
    	byte |= PM_SERIRQ_MODE;

@@ -91,8 +93,7 @@
    /* Initialize i8254 timers */
    setup_i8254();

-	if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
-		setup_serirq();
+	setup_serirq();
 }

static void lpc_read_resources(struct device *dev)