[M] Change in coreboot[master]: soc/intel/xeon_sp: Improve final MTRR solution

[Jonathan Zhang (Code Review)]

Attention is currently required from: Arthur Heymans, Johnny Lin, Christian Walter, Tim Chu.

Hello Arthur Heymans, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/71142

to look at the new patch set (#3).

Change subject: soc/intel/xeon_sp: Improve final MTRR solution
......................................................................

soc/intel/xeon_sp: Improve final MTRR solution

If cbmem_top is not 1M aligned there will be a hole between DPR base
and cbmem_top that the allocator will consider as unassigned memory.
Resources could incorrectly be assigned to that region and the final
MTRR solution will also try to skip that hole, therefore using a lot
more variable MTRRs than needed.

TESTED on Archer City 2S system: Uses 1 variable MTRR in the final
setup instead of 7.

Change-Id: I198f8d83bcfcdca3a770bd7f9a7060d5782a49fe
Signed-off-by: Arthur Heymans 
Signed-off-by: Jonathan Zhang 
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 47 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/71142/3