Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80415?usp=email )
(
3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_config ......................................................................
soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_config
This function turns off gpp_clk for the devices which are disabled, and adds the code to fix up the clock configuration depending on dxio descriptors. Also this brings glinda in line with cezanne, mendocino, phoenix and picasso. This also prepares glinda to use the common function gpp_clk_setup_common.
Change-Id: Id66d1b7f0d8ec9a7cbd378ad6ad7d68eeab531f0 Signed-off-by: Varshit Pandya pandyavarshit@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/80415 Reviewed-by: Anand Vaikar a.vaikar2021@gmail.com Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/chip.h M src/soc/amd/glinda/fch.c 3 files changed, 7 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Anand Vaikar: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index a042ea2..8a6649a 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -75,6 +75,7 @@ select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP diff --git a/src/soc/amd/glinda/chip.h b/src/soc/amd/glinda/chip.h index d33261f..085bac5 100644 --- a/src/soc/amd/glinda/chip.h +++ b/src/soc/amd/glinda/chip.h @@ -7,6 +7,7 @@
#include <amdblocks/chip.h> #include <amdblocks/i2c.h> +#include <amdblocks/pci_clk_req.h> #include <gpio.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -92,11 +93,7 @@
/* The array index is the general purpose PCIe clock output number. Values in here aren't the values written to the register to have the default to be always on. */ - enum { - GPP_CLK_ON, /* GPP clock always on; default */ - GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ - GPP_CLK_OFF, /* GPP clk off */ - } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; + enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
/* performance policy for the PCIe links: power consumption vs. link speed */ enum { diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index 93597c9..bb03ad4 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -6,6 +6,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> +#include <amdblocks/pci_clk_req.h> #include <amdblocks/reset.h> #include <amdblocks/smi.h> #include <assert.h> @@ -130,7 +131,7 @@ /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { - const struct soc_amd_glinda_config *cfg = config_of_soc(); + struct soc_amd_glinda_config *cfg = config_of_soc();
/* look-up table to be able to iterate over the PCIe clock output settings */ const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { @@ -145,6 +146,8 @@
uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
+ pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], + ARRAY_SIZE(cfg->gpp_clk_config)); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); /*