Attention is currently required from: Angel Pons, Felix Singer, Matt DeVillier, Nicholas Chin, Nico Huber.
Joel Linn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81368?usp=email )
Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) ......................................................................
Patch Set 6:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81368/comment/8bbfc85a_5c986163 : PS5, Line 12: All peripherals should work. : Automatic fan control as well as S3 are working. : The board was tested to boot Linux and Windows. EHCI debug is untested. : When using MrChromebox edk2 with secure boot build in, the board will : hang on each boot for about 20 seconds before continuing.
Should probably prefix these with bullet points, e.g. `* `.
Done
File src/mainboard/hp/pro_3500_series/Makefile.mk:
PS5:
Add a blank line between each stage for better distinction.
Done
File src/mainboard/hp/pro_3500_series/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/81368/comment/9103c5eb_c6969dd0 : PS5, Line 11: device ref host_bridge on end
Enabled in chipset devicetree
Done
https://review.coreboot.org/c/coreboot/+/81368/comment/088df9f1_c5293d57 : PS5, Line 16: register "docking_supported" = "0"
Doesn't have any effect, set to 0 anyway.
Done
https://review.coreboot.org/c/coreboot/+/81368/comment/b779d368_9619434e : PS5, Line 27: device ref mei1 on end
Enabled in chipset devicetree
Done
https://review.coreboot.org/c/coreboot/+/81368/comment/71218bbc_ad3b8271 : PS5, Line 36: # LPC bridge
Remove superfluous comment
Done
https://review.coreboot.org/c/coreboot/+/81368/comment/46934328_9cb4ecb2 : PS5, Line 96: device ref smbus on end
Enabled in chipset devicetree
Done