Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56175 )
Change subject: soc/intel/alderlake: Add (and fix) devices in IRQ table ......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/56175/comment/b9fe3f61_c3a8d468 PS2, Line 51: FIXED_INT_PIRQ
EDS and both say INT_LINE is RW for IGD and IPU (and indeed, they appear programmable from lspci's reporting), but empirically, S0ix fails if they are not set to 16 (their pin is RO set to PCI_INT_A).
Could it be some bad assumption in FSP?
The CPU_6 slot is just more PCIe RPs, so are programmed the same as the the PCH side (according to their `function number % 4`)
That makes sense. I was curious mostly about the non-PCIE RP devices as to how the decision was made:
IGD, IPU -> Fixed int and pirq UART0, UART1, Tracehub -> Fixed int
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Furquan Shaikh (Code Review)