[S] Change in coreboot[master]: soc/intel/apollolake: Fix FSP SATA speed limit configuraion

[Mario Scheithauer (Code Review)]

Attention is currently required from: Eric Lai, Felix Singer, Jan Samek, Sean Rhodes, Werner Zeh.

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75820?usp=email )

Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
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Patch Set 8:

(3 comments)

Patchset:

PS7:
> Is there anything on which the SATA speed depends on or what could limit it?

The signal quality was measured with an oscilloscope and it was found that our boards are at the permissible limit with Gen 3. To be on the safe side, it was decided to switch to the next lower speed.

File src/soc/intel/apollolake/ahci.c:

https://review.coreboot.org/c/coreboot/+/75820/comment/6f3010c8_0ff5cc4c :
PS7, Line 12: 	if (speed == SATA_DEFAULT)
            :
> nit: I wouldn't care about default values and just write the bits in any case.

Done

File src/soc/intel/apollolake/include/soc/ahci.h:

https://review.coreboot.org/c/coreboot/+/75820/comment/bbb13ec4_2376a701 :
PS7, Line 11: 0x00F00000
> make it lowercase

Done