Change in coreboot[master]: google/cyan: Configure WLAN_CLKREQ as GPIO and always assert low

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27762

Change subject: google/cyan: Configure WLAN_CLKREQ as GPIO and always assert low
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google/cyan: Configure WLAN_CLKREQ as GPIO and always assert low

Adapted from chromium commit adcb858
[cyan: Configure WLAN_CLKREQ as GPIO and always assert low]

This is a workaround for issue b/35648315 as proposed by Intel to
ensure that WLAN_CLKREQ always stays low.

BUG=b:35648315

Original-Change-Id: I178b3e4fbf74cf08eadfa8bd31b80b018f330e77
Original-Signed-off-by: Furquan Shaikh 
Original-Reviewed-on: https://chromium-review.googlesource.com/1055652
Original-Reviewed-by: Rajat Jain 
Original-Tested-by: Rajat Jain

Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938
Signed-off-by: Matt DeVillier 
---
M src/mainboard/google/cyan/variants/cyan/gpio.c
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/27762/1

diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c
index 4139f76..bf869fe 100644
--- a/src/mainboard/google/cyan/variants/cyan/gpio.c
+++ b/src/mainboard/google/cyan/variants/cyan/gpio.c
@@ -136,7 +136,9 @@
    Native_M1, /* 90 PCIE_CLKREQ0B */
    GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */
    Native_M1, /* 92 GP_SSP_2_CLK */
-	NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
+	/* Workaround for issue b/35648315: Program this as GPIO and always
+	   assert it low. */
+	GPIO_OUT_LOW, /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
    Native_M1, /* 94 GP_SSP_2_RXD */
    GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
    	/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */