Change in coreboot[master]: soc/intel/alderlake: Disable VT-d for early silicons

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59191 )

Change subject: soc/intel/alderlake: Disable VT-d for early silicons
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soc/intel/alderlake: Disable VT-d for early silicons

VT-d needs to disabled for early silicons as it results in a
CPU hard hang.

BUG=b:197177091
Test=Boot brya to OS with no hang

Signed-off-by: Meera Ravindranath 
Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/59191/1

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index be71a02..bfca66d 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -3,6 +3,7 @@
 #include <assert.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/intel/cpu_ids.h>
 #include <device/device.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
@@ -259,6 +260,11 @@
 static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg,
    	const struct soc_intel_alderlake_config *config)
 {
+
+	if(cpu_get_cpuid() == CPUID_ALDERLAKE_A0 || CPUID_ALDERLAKE_A1) {
+		m_cfg->VtdDisable = 1;
+		return;
+	} 
    m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS;
    m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS;
    m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS;