Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32017
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
mb/google/hatch: Enable FP MCU
AP communicates with FP MCU through gspi1.
BUG=b:126455006 BRANCH=None TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg FP MCU fw is not ready yet, so not much testing to be done yet.
Signed-off-by: Shelley Chen shchen@google.com
Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32017/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 0299ded..28cc888 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -25,6 +25,7 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | + #| GSPI1 | FP MCU | #| I2C0 | Touchpad | #| I2C1 | Touch screen | #| I2C4 | Audio | @@ -34,6 +35,10 @@ .speed_mhz = 1, .early_init = 1, }, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, @@ -290,7 +295,17 @@ device spi 0 on end end end # GSPI #0 - device pci 1e.3 off end # GSPI #1 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" # GPP_A23 + device spi 1 on end + end # FPMCU + end # GSPI #1 device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end
Shelley Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
mb/google/hatch: Enable FP MCU
AP communicates with FP MCU through gspi1.
BUG=b:126455006 BRANCH=None TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg FP MCU fw is not ready yet, so not much testing to be done yet.
Signed-off-by: Shelley Chen shchen@google.com
Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32017/2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/32017/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/32017/2/src/mainboard/google/hatch/variants/... PS2, Line 299: chip drivers/spi/acpi Should the reset_gpio be hooked up here as well? (GPP_A12) ?
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/32017/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/32017/2/src/mainboard/google/hatch/variants/... PS2, Line 299: chip drivers/spi/acpi
Should the reset_gpio be hooked up here as well? (GPP_A12) ?
I am not sure tbh. We did not do this for nami. Do we need it hooked up, Furquan?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/32017/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/32017/2/src/mainboard/google/hatch/variants/... PS2, Line 299: chip drivers/spi/acpi
I am not sure tbh. We did not do this for nami. […]
Actually, there is nothing in the kernel that actually uses it. So, currently we don't need to export reset gpio.
https://review.coreboot.org/#/c/32017/2/src/mainboard/google/hatch/variants/... PS2, Line 305: GPE0_DW0_23 Doesn't this cause failures to enter S0ix since GPP_A23 is not configured with INVERT?
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/32017/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/32017/2/src/mainboard/google/hatch/variants/... PS2, Line 305: GPE0_DW0_23
Doesn't this cause failures to enter S0ix since GPP_A23 is not configured with INVERT?
I did not verify S0ix, but you are probably correct. But as we only have 1 gpio for FPMCU_PCH_INT_ODL, this means that we'll have to disable wake on FP until the ITSS bug is fixed?
Hello Tim Wawrzynczak, Nicolas Norvez, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32017
to look at the new patch set (#3).
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
mb/google/hatch: Enable FP MCU
AP communicates with FP MCU through gspi1.
BUG=b:126455006 BRANCH=None TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg FP MCU fw is not ready yet, so not much testing to be done yet.
Signed-off-by: Shelley Chen shchen@google.com
Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 19 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32017/3
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32017/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/32017/2/src/mainboard/google/hatch/variants/... PS2, Line 305: GPE0_DW0_23
I did not verify S0ix, but you are probably correct. […]
Ok, let's get rid of wake on FP until ITSS is fixed.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32017/3/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/32017/3/src/mainboard/google/hatch/variants/... PS3, Line 38: .gspi[1] = { : .speed_mhz = 1, : .early_init = 1, : }, Why is this required? We don't talk to the FP device in firmware.
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32017/3/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/32017/3/src/mainboard/google/hatch/variants/... PS3, Line 38: .gspi[1] = { : .speed_mhz = 1, : .early_init = 1, : },
Why is this required? We don't talk to the FP device in firmware.
I thought that was how to explicitly set the fp clk to 1 mhz.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32017/3/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/32017/3/src/mainboard/google/hatch/variants/... PS3, Line 38: .gspi[1] = { : .speed_mhz = 1, : .early_init = 1, : },
I thought that was how to explicitly set the fp clk to 1 mhz.
if you are talking to it in firmware.
Hello Tim Wawrzynczak, build bot (Jenkins), Nicolas Norvez, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32017
to look at the new patch set (#4).
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
mb/google/hatch: Enable FP MCU
AP communicates with FP MCU through gspi1.
BUG=b:126455006 BRANCH=None TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg FP MCU fw is not ready yet, so not much testing to be done yet.
Signed-off-by: Shelley Chen shchen@google.com
Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 15 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32017/4
Hello Tim Wawrzynczak, build bot (Jenkins), Nicolas Norvez, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32017
to look at the new patch set (#5).
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
mb/google/hatch: Enable FP MCU
AP communicates with FP MCU through gspi1.
BUG=b:126455006 BRANCH=None TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg FP MCU fw is not ready yet, so not much testing to be done yet.
Signed-off-by: Shelley Chen shchen@google.com
Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 15 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32017/5
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/32017/3/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/32017/3/src/mainboard/google/hatch/variants/... PS3, Line 38: .gspi[1] = { : .speed_mhz = 1, : .early_init = 1, : },
if you are talking to it in firmware.
Speed for the kernel is passed in here: https://cs.corp.google.com/chromeos_public/src/third_party/coreboot/src/driv...
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32017 )
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
mb/google/hatch: Enable FP MCU
AP communicates with FP MCU through gspi1.
BUG=b:126455006 BRANCH=None TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg FP MCU fw is not ready yet, so not much testing to be done yet.
Signed-off-by: Shelley Chen shchen@google.com
Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32017 Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 15 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2b18b3b..0399dc1 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -25,6 +25,7 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | + #| GSPI1 | FP MCU | #| I2C0 | Touchpad | #| I2C1 | Touch screen | #| I2C4 | Audio | @@ -321,7 +322,16 @@ device spi 0 on end end end # GSPI #0 - device pci 1e.3 off end # GSPI #1 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 93e0af1..73d6645 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -62,7 +62,10 @@ PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), /* A22 : FPMCU_PCH_BOOT0 */ PAD_CFG_GPO(GPP_A22, 0, DEEP), - /* A23 : FPMCU_PCH_INT_ODL */ + /* A23 : FPMCU_PCH_INT_ODL + * TODO Configure it back to invert mode, when + * ITSS IPCx configuration is fixed in FSP. + */ PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, NONE),
/* B0 : CORE_VID0 */