PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36319 )
Change subject: mb/intel/saddlebrook: Enable serial port on SIO ......................................................................
mb/intel/saddlebrook: Enable serial port on SIO
Enable saddlebrook board Serial port on SuperIO by selecting DRIVERS_UART_8250IO.
TEST=Build, Boot saddlebrook board and verified serial logs.
Change-Id: Ic7b3416f281bfd91416c987c5a720ffac0c89d45 Signed-off-by: Praveen Hodagatta Pranesh praveenx.hodagatta.pranesh@intel.com --- M src/mainboard/intel/saddlebrook/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/36319/1
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 934c15a..cd18541 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -24,7 +24,6 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select INTEL_LPSS_UART_FOR_CONSOLE select SKYLAKE_SOC_PCH_H select SOC_INTEL_SKYLAKE select SUPERIO_NUVOTON_NCT6776
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36319 )
Change subject: mb/intel/saddlebrook: Enable serial port on SIO ......................................................................
Patch Set 1: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36319 )
Change subject: mb/intel/saddlebrook: Enable serial port on SIO ......................................................................
Patch Set 1: Code-Review+1
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36319 )
Change subject: mb/intel/saddlebrook: Enable serial port on SIO ......................................................................
mb/intel/saddlebrook: Enable serial port on SIO
Enable saddlebrook board Serial port on SuperIO by selecting DRIVERS_UART_8250IO.
TEST=Build, Boot saddlebrook board and verified serial logs.
Change-Id: Ic7b3416f281bfd91416c987c5a720ffac0c89d45 Signed-off-by: Praveen Hodagatta Pranesh praveenx.hodagatta.pranesh@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36319 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Michael Niewöhner --- M src/mainboard/intel/saddlebrook/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 3fb694a..1e430f9 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -24,7 +24,6 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select INTEL_LPSS_UART_FOR_CONSOLE select SKYLAKE_SOC_PCH_H select SOC_INTEL_SKYLAKE select SUPERIO_NUVOTON_NCT6776
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Michael Niewöhner (Code Review) -
Nico Huber (Code Review)
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PraveenX Hodagatta Pranesh (Code Review)