[S] Change in coreboot[master]: soc/intel/mtl: [TEST] Read R_DCI_PCR_ECTRL

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74578 )

Change subject: soc/intel/mtl: [TEST] Read R_DCI_PCR_ECTRL
......................................................................

soc/intel/mtl: [TEST] Read R_DCI_PCR_ECTRL

Signed-off-by: Sridhar Siricilla 
Change-Id: Ie2f52acfadc44307b91a7528e5d796ddeef5ed1d
---
M src/soc/intel/meteorlake/bootblock/soc_die.c
M src/soc/intel/meteorlake/include/soc/pcr_ids.h
2 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/74578/1

diff --git a/src/soc/intel/meteorlake/bootblock/soc_die.c b/src/soc/intel/meteorlake/bootblock/soc_die.c
index f5a3c91..3c44025 100644
--- a/src/soc/intel/meteorlake/bootblock/soc_die.c
+++ b/src/soc/intel/meteorlake/bootblock/soc_die.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <console/console.h>
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
@@ -136,6 +137,12 @@
    }
 }

+#define R_DCI_PCR_ECTRL	0x00000004
+static void dci_log_dbgctrl(void)
+{
+	printk(BIOS_DEBUG, "R_DCI_PCR_ECTRL 0x%x\n", pcr_read32(PID_DCI, R_DCI_PCR_ECTRL);
+}
+
 void bootblock_soc_die_init(void)
 {
    /*
@@ -151,4 +158,7 @@

/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
    tco_configure();
+
+
+	dci_log_dbgctrl();
 }
diff --git a/src/soc/intel/meteorlake/include/soc/pcr_ids.h b/src/soc/intel/meteorlake/include/soc/pcr_ids.h
index 0ef9f30..819fa55 100644
--- a/src/soc/intel/meteorlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/meteorlake/include/soc/pcr_ids.h
@@ -28,5 +28,6 @@
 #define PID_ISCLK	0x64
 #define PID_DMI		0x88
 #define PID_IOM		0xAA
+#define PID_DCI		0xCF

#endif