Change in coreboot[master]: src: use ARRAY_SIZE where possible

[Patrick Georgi (Code Review)]

Attention is currently required from: Werner Zeh, Patrick Rudolph, HAOUAS Elyes.
Hello build bot (Jenkins), Angel Pons, Werner Zeh, Patrick Rudolph, HAOUAS Elyes,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/50594

to look at the new patch set (#3).

Change subject: src: use ARRAY_SIZE where possible
......................................................................

src: use ARRAY_SIZE where possible

Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci

Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi 
---
M src/arch/x86/cpu.c
M src/cpu/x86/smm/smm_module_loaderv2.c
M src/mainboard/amd/persimmon/mainboard.c
M src/mainboard/asus/am1i-a/mainboard.c
M src/mainboard/bap/ode_e20XX/mainboard.c
M src/mainboard/biostar/am1ml/mainboard.c
M src/mainboard/elmex/pcm205400/mainboard.c
M src/mainboard/gizmosphere/gizmo2/mainboard.c
M src/mainboard/google/foster/sdram_configs.c
M src/mainboard/google/nyan/sdram_configs.c
M src/mainboard/google/nyan_big/sdram_configs.c
M src/mainboard/google/nyan_blaze/sdram_configs.c
M src/mainboard/google/smaug/sdram_configs.c
M src/mainboard/hp/abm/mainboard.c
M src/mainboard/jetway/nf81-t56n-lf/mainboard.c
M src/mainboard/pcengines/apu1/mainboard.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/northbridge/intel/e7505/raminit.c
M src/northbridge/intel/ironlake/raminit.c
M src/soc/intel/braswell/tsc_freq.c
M src/soc/intel/denverton_ns/gpio_dnv.c
M src/soc/qualcomm/sc7180/display/dsi_phy.c
M src/vendorcode/amd/agesa/common/agesa-entry.c
M src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
M src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
M src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
M src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c
M src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c
M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
M src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c
M src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c
M src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c
M src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c
M src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
M src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c
M src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c
M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c
M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c
M src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c
M src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c
M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c
M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c
M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c
M src/vendorcode/amd/cimx/sb900/SBPort.c
M src/vendorcode/amd/cimx/sb900/Sata.c
M src/vendorcode/amd/cimx/sb900/SbCmn.c
M src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c
M src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c
M src/vendorcode/cavium/bdk/libdram/libdram-config-load.c
74 files changed, 214 insertions(+), 208 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50594/3