[M] Change in coreboot[main]: intel/alderlake: Add helper functions for Power Management

[Sean Rhodes (Code Review)]

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eric Lai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Nico Huber, Paul Menzel, Subrata Banik.

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/81638?usp=email )

Change subject: intel/alderlake: Add helper functions for Power Management
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Patch Set 18:

(3 comments)

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/81638/comment/b4355d05_875968cd?usp... :
PS4, Line 799: };
> Doh, it look me ages to see why - CPU ports have a different default which was what broke things for […]

Done

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/81638/comment/68edf909_d18b2afe?usp... :
PS15, Line 507: if (rp_cfg->pcie_rp_aspm == 0)
              : 		s_cfg->PcieRpAspm[index] = 4;
              : 	else
              : 		s_cfg->PcieRpAspm[index] = rp_cfg->pcie_rp_aspm - 1;
> I added the prefix because there's functions elsewhere (common code?) with the same name.

Added prefixes but will do a follow up patch to move it to common code so mtl can share. Maybe other platforms too, if there's a way to handle not having CPU RPs

https://review.coreboot.org/c/coreboot/+/81638/comment/8ec3e67e_63c6ace9?usp... :
PS15, Line 519: if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
              : 		s_cfg->PcieRpL1Substates[index] = 0;
              : 	else if (rp_cfg->PcieRpL1Substates == 0)
              : 		s_cfg->PcieRpL1Substates[index] = 3;
              : 	else
              : 		s_cfg->PcieRpL1Substates[index] = rp_cfg->PcieRpL1Substates - 1;
> I would make a helper function for this: […]

Done