Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54959 )

Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
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Patch Set 12:

(2 comments)

File src/soc/intel/elkhartlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/54959/comment/0df152a3_8b2e04e6 
PS12, Line 54: 	_Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >=
             : 			ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!");
             : 	memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode,
             : 		sizeof(config->SerialIoI2cMode));
             :
> why? just why? see diskussion here about making the devicetree a mess https://review.coreboot. […]

Yes soc device tree is a better idea. what is your take here?

https://review.coreboot.org/c/coreboot/+/54959/comment/bb32b710_74430b4d 
PS12, Line 65: 	params->PchSerialIoI2cSclPinMux[4] = 0x1B44AC09;	//GPIO native mode for GPP_H9
             : 	params->PchSerialIoI2cSdaPinMux[4] = 0x1B44CC08;	//GPIO native mode for GPP_H8
             :
> board specific settings hardcoded?!

Yeah, unfortunately EHL does not have UPD setting to bypass GPIO settings in FSP :( which means that some gpio will be overwritten in FSP even it is set in coreboot. I think EHL is the last project to have this flaw, so i did not come out with another full solution.