Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3213
-gerrit
commit f4586b020b75b3d39bda4b5181292f456de700f7 Author: Stefan Reinauer reinauer@chromium.org Date: Mon May 6 18:05:39 2013 -0700
copy_and_run: drop boot_complete parameter
Since this parameter is not used anymore, drop it from all calls to copy_and_run()
Change-Id: Ifba25aff4b448c1511e26313fe35007335aa7f7a Signed-off-by: Stefan Reinauer reinauer@google.com --- src/arch/x86/include/arch/stages.h | 3 +-- src/arch/x86/init/crt0_romcc_epilogue.inc | 5 ----- src/arch/x86/lib/c_start.S | 1 - src/arch/x86/lib/cbfs_and_run.c | 13 ++++--------- src/arch/x86/lib/stages.c | 2 -- src/cpu/amd/car/post_cache_as_ram.c | 2 +- src/cpu/amd/geode_gx2/cache_as_ram.inc | 4 ---- src/cpu/amd/geode_lx/cache_as_ram.inc | 4 ---- src/cpu/intel/car/cache_as_ram.inc | 5 ----- src/cpu/intel/car/cache_as_ram_ht.inc | 5 ----- src/cpu/intel/haswell/romstage.c | 2 +- src/cpu/intel/model_206ax/cache_as_ram.inc | 5 ----- src/cpu/intel/model_6ex/cache_as_ram.inc | 5 ----- src/cpu/via/car/cache_as_ram.inc | 5 ----- src/mainboard/amd/dinar/romstage.c | 2 +- src/mainboard/amd/inagua/romstage.c | 2 +- src/mainboard/amd/parmer/romstage.c | 2 +- src/mainboard/amd/persimmon/romstage.c | 2 +- src/mainboard/amd/south_station/romstage.c | 2 +- src/mainboard/amd/thatcher/romstage.c | 2 +- src/mainboard/amd/torpedo/romstage.c | 2 +- src/mainboard/amd/union_station/romstage.c | 2 +- src/mainboard/asrock/e350m1/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/emulation/qemu-x86/cache_as_ram.inc | 5 ----- src/mainboard/lippert/frontrunner-af/romstage.c | 2 +- src/mainboard/lippert/toucan-af/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/romstage.c | 2 +- src/mainboard/supermicro/h8scm/romstage.c | 2 +- src/mainboard/tyan/s8226/romstage.c | 2 +- 30 files changed, 22 insertions(+), 74 deletions(-)
diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 0d00144..3dea427 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -22,6 +22,5 @@
#include <arch/cpu.h>
-void asmlinkage copy_and_run(unsigned cpu_reset); -void asmlinkage copy_and_run_ap_code_in_car(unsigned ret_addr); +void asmlinkage copy_and_run(void); #endif diff --git a/src/arch/x86/init/crt0_romcc_epilogue.inc b/src/arch/x86/init/crt0_romcc_epilogue.inc index b19f968..419418d 100644 --- a/src/arch/x86/init/crt0_romcc_epilogue.inc +++ b/src/arch/x86/init/crt0_romcc_epilogue.inc @@ -7,17 +7,12 @@ */ #include <cpu/x86/post_code.h>
- /* clear boot_complete flag */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* clear direction flag */
- movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run
.Lhlt: diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index e65dc0a..6c78e0d 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -73,7 +73,6 @@ _start: #if CONFIG_GDB_WAIT call gdb_stub_breakpoint #endif - /* The boot_complete flag has already been pushed */ call hardwaremain /* NOTREACHED */ .Lhlt: diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 2db50a1..6379842 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -22,7 +22,7 @@ #include <arch/stages.h> #include <timestamp.h>
-static void cbfs_and_run_core(const char *filename, unsigned ebp) +static void cbfs_and_run_core(const char *filename) { u8 *dst;
@@ -35,17 +35,12 @@ static void cbfs_and_run_core(const char *filename, unsigned ebp) timestamp_add_now(TS_END_COPYRAM); print_debug("Jumping to image.\n"); __asm__ volatile ( - "movl %%eax, %%ebp\n" "jmp *%%edi\n" - :: "a"(ebp), "D"(dst) + :: "D"(dst) ); }
-void asmlinkage copy_and_run(unsigned cpu_reset) +void asmlinkage copy_and_run(void) { - // FIXME fix input parameters instead normalizing them here. - if (cpu_reset == 1) cpu_reset = -1; - else cpu_reset = 0; - - cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset); + cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram"); } diff --git a/src/arch/x86/lib/stages.c b/src/arch/x86/lib/stages.c index a6a232a..2da66d3 100644 --- a/src/arch/x86/lib/stages.c +++ b/src/arch/x86/lib/stages.c @@ -20,8 +20,6 @@ static void skip_romstage(void) { asm volatile ( - "/* set the boot_complete flag */\n" - "movl $0xffffffff, %%ebp\n" "jmp __main\n" ); } diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 861948f..68e7c09 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -165,7 +165,7 @@ static void post_cache_as_ram(void) set_sysinfo_in_ram(1); // So other core0 could start to train mem
/*copy and execute coreboot_ram */ - copy_and_run(0); + copy_and_run(); /* We will not return */
print_debug("should not be here -\n"); diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 941d507..6a107fe 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -182,8 +182,6 @@ done_cache_as_ram_main: xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ movl %eax, %cr0
- /* clear boot_complete flag */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE)
@@ -197,8 +195,6 @@ __main: * the location it is compiled to run at. * Normally this is copying from FLASH ROM to RAM. */ - movl %ebp, %esi - pushl %esi call copy_and_run
.Lhlt: diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index 3146fd2..d2c2415 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -208,8 +208,6 @@ done_cache_as_ram_main: xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ movl %eax, %cr0
- /* clear boot_complete flag */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE)
@@ -223,8 +221,6 @@ __main: * the location it is compiled to run at. * Normally this is copying from FLASH ROM to RAM. */ - movl %ebp, %esi - pushl %esi call copy_and_run
.Lhlt: diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 781e480..1ea50b8 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -357,17 +357,12 @@ lout: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0
- /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run
.Lhlt: diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 9ef69ad..8a845e9 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -431,17 +431,12 @@ no_msr_11e:
post_code(0x3c)
- /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run
.Lhlt: diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index ff57584..ef3bf11 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -326,7 +326,7 @@ void romstage_after_car(void) #endif
/* Load the ramstage. */ - copy_and_run(0); + copy_and_run(); }
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 4202da9..2652cb7 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -316,17 +316,12 @@ __acpi_resume_backup_done:
post_code(0x3d)
- /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run
.Lhlt: diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index b8222e1..50fab35 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -225,17 +225,12 @@ clear_mtrrs:
post_code(0x3c)
- /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run
.Lhlt: diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 1af8ecc..17b4b83 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -264,17 +264,12 @@ testok: movl %eax, %cr0 invd
- /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run
.Lhlt: diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index a9bcde0..77f73e2 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("done\n");
post_code(0x44); - copy_and_run(0); + copy_and_run();
post_code(0x45); // Should never see this post code. } diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index d46d4ab..3474d76 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254();
post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 25f14e8..7cd7638 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 ();
post_code(0x50); - copy_and_run(0); + copy_and_run();
post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index eedae56..b748a90 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 ();
post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index c273344..970046d 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n");
post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 1f3e86d..601aa7e 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -168,7 +168,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 ();
post_code(0x50); - copy_and_run(0); + copy_and_run();
post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 8edba80..bbcd764 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x43); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run returned!\n");
post_code(0x44); // Should never see this post code. diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 9045c04..93aa327 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -106,7 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n");
post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 96339b9..7e806fa 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -122,7 +122,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254();
post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index c2fc75e..b7bcf43 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -199,7 +199,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 ();
post_code(0x50); - copy_and_run(0); + copy_and_run();
post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/emulation/qemu-x86/cache_as_ram.inc b/src/mainboard/emulation/qemu-x86/cache_as_ram.inc index 1a7d8af..11ac91d 100644 --- a/src/mainboard/emulation/qemu-x86/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-x86/cache_as_ram.inc @@ -80,17 +80,12 @@ __acpi_resume_backup_done:
post_code(0x3d)
- /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run
.Lhlt: diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index b04b0ea..8913568 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -182,7 +182,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 ();
post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index b5ff31f..ebc4d0e 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -182,7 +182,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_i8254 ();
post_code(0x50); - copy_and_run(0); + copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */ diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 45422bb..0d25113 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -128,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("done\n");
post_code(0x51); - copy_and_run(0); + copy_and_run();
/* We will not return, Should never see this message and post code. */ print_debug("should not be here -\n"); diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 3219fda..5dccf78 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("done\n");
post_code(0x51); - copy_and_run(0); + copy_and_run();
/* We will not return, Should never see this message and post code. */ print_debug("should not be here -\n"); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index ee16ceb..b4f9523 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x51); setup_i8259 (); setup_i8254 (); - copy_and_run(0); + copy_and_run();
/* We will not return, Should never see this message and post code. */ print_debug("should not be here -\n");
-
Stefan Reinauer