Change in coreboot[master]: mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematics

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49964 )

Change subject: mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematics
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mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematics

1. GPP_E5 =>  Remove unused GPIOs
2. GPP_H12, GPP_H13 => Program the correct Native Functions for GPIO

Change-Id: I588a8c1153eaa1bf818a081c6c5d18a669017d95
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49964
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Furquan Shaikh 
---
M src/mainboard/intel/adlrvp/gpio.c
1 file changed, 3 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index 3131cc0..1996683 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -226,10 +226,9 @@
    /* SMB_DATA */
    PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),

-	/* SATADevSlpPin to GPIO pin mapping */
-	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
-	/* SATA DIRECT DEVSLP*/
-	PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5),
+	/* SATA DEVSLP */
+	PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),

/* SATA LED pin */
    PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),