New patch to review for coreboot: skylake: provide clarification for FADT gpe0_blk_len

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11205

-gerrit

commit 63734fd6ddceb1e881764eb1ab3044ea55aab6a3
Author: Aaron Durbin 
Date:   Fri Aug 7 23:00:22 2015 -0500

skylake: provide clarification for FADT gpe0_blk_len

Instead of using a hard-coded value leverage the existing
    definitions to perform GPE0 block length calculations. There
    are 4 pairs of 32-bit status/enable registers.

BUG=chrome-os-partner:43522
    BRANCH=None
    TEST=Built and booted glados.

Original-Change-Id: I14d08298b5750c91ce0ac3fa33569813396f7089
    Original-Signed-off-by: Aaron Durbin 
    Original-Reviewed-on: https://chromium-review.googlesource.com/291932
    Original-Reviewed-by: Duncan Laurie

Change-Id: I127f026f15180fa79625d4cad96d5e35f85e5090
    Signed-off-by: Aaron Durbin 
---
 src/soc/intel/skylake/acpi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 1b193c7..87d4eb0 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -222,7 +222,8 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt)
    fadt->pm1_cnt_len = 2;
    fadt->pm2_cnt_len = 1;
    fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 32;
+	/* There are 4 GPE0 STS/EN pairs each 32 bits wide. */
+	fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
    fadt->gpe1_blk_len = 0;
    fadt->gpe1_base = 0;
    fadt->cst_cnt = 0;