New patch to review for coreboot: 345e1ab Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 ms

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9478

-gerrit

commit 345e1ab3294699829eb26c0afba73699d1f1e48b
Author: Kevin Hsieh 
Date:   Wed Nov 26 03:08:18 2014 +0800

Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 ms

Using REG_PCI_POLL32 to check if the LINK is active with 50ms timeout.

BRANCH=none
    BUG=chromium:431169
    TEST=Test on Enguarde, compile ok and boot OS

Change-Id: If98ab4e31d17ec4e62d68b93edcec6d9aee87367
    Signed-off-by: Stefan Reinauer 
    Original-Commit-Id: cf692ae9aebb43ab46cb07d36b62b300b16be1dc
    Original-Change-Id: I490e6ffa40979628edf52a7444808b6d25a6e83d
    Original-Signed-off-by: Kevin Hsieh 
    Original-Reviewed-on: https://chromium-review.googlesource.com/231777
    Original-Reviewed-by: Shawn Nematbakhsh 
---
 src/soc/intel/baytrail/pcie.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index ff48913..1870158 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -230,6 +230,19 @@ static void byt_pcie_enable(device_t dev)
    southcluster_enable_dev(dev);
 }

+static unsigned int byt_pciexp_scan_bridge(device_t dev, unsigned int max)
+{
+	static const struct reg_script wait_for_link_active[] = {
+		REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000),
+		REG_SCRIPT_END,
+	};
+
+	/* wait for Link Active with 50ms timeout */
+	reg_script_run_on_dev(dev, wait_for_link_active);
+
+	return do_pci_scan_bridge(dev, max, pciexp_scan_bus);
+}
+
 static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did)
 {
    uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff);
@@ -248,7 +261,7 @@ static struct device_operations device_ops = {
    .set_resources		= pci_dev_set_resources,
    .enable_resources	= pci_bus_enable_resources,
    .init			= byt_pcie_init,
-	.scan_bus		= pciexp_scan_bridge,
+	.scan_bus		= byt_pciexp_scan_bridge,
    .enable			= byt_pcie_enable,
    .ops_pci		= &pcie_root_ops,
 };