Change in coreboot[master]: src/drivers/intel/fsp2_0: Added FSP_S component to VBOOT Stage Verifi... - coreboot-gerrit

15 Nov 2021


      Julius Werner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32155 )
Change subject: src/drivers/intel/fsp2_0: Added FSP_S component to VBOOT Stage Verification.                           FSP_S component will be verified in RAMSTAGE.
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Abandoned
This direction of development was abandoned and instead the CONFIG_CBFS_VERIFICATION effort is intended to solve this use case. See CB:32159 for original discussion.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifefad96b54388143fecb56f0402c3b627ae6350d
Gerrit-Change-Number: 32155
Gerrit-PatchSet: 2
Gerrit-Owner: Amol N Sukerkar amol.n.sukerkar@intel.com
Gerrit-Reviewer: Amol N Sukerkar amol.n.sukerkar@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Philipp Deppenwiese zaolin.daisuki@gmail.com
Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Julius Werner jwerner@chromium.org
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