[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines

[Cliff Huang (Code Review)]

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )

Change subject: soc/intel/ptl: Add GPE1 defines
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Patch Set 6:

(1 comment)

File src/soc/intel/pantherlake/include/soc/gpe.h:

https://review.coreboot.org/c/coreboot/+/84297/comment/293f0097_1a38e472?usp... :
PS4, Line 30: 146
> > GPE1[0] starts from 0x80 (i.e. […]

true. Although the GPE1 could be placed starting after 0x80, we don't have much choice but put GPE1 right after GPE0. The maximum GPE event number is 256. GPE0 occupies 128 across all SOCs and PTL GPE1 has three 32-bit blocks, so only another 32-bit left that a SOC can extend in the future. It should be okay to always put it immediately after GPE0. But, detailed comment will be helpful to explain how the numbers are derived from. In addition, there are several unused reserved bits in between GPE1 bits, so they are not incremental numbers. Short comments are placed at the end to indicate its corresponding _L[nn] event method name.