Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N - coreboot-gerrit

20 Dec 2021


      Attention is currently required from: Anilkumar N, Maulik V Vaghela, Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D.
Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59937 )
Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
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Patch Set 9:
(1 comment)
File src/mainboard/intel/adlrvp/early_gpio_n.c:
https://review.coreboot.org/c/coreboot/+/59937/comment/12e9aa27_3948a4b5 
PS7, Line 19: 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1),
...
Do we really need to configure CPU PCIe vGPIO considering number of CPU root port are 0? […]
Since there are no CPU Root Ports for ADL-N. These CPU PCIe vGPIO config is not required.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca
Gerrit-Change-Number: 59937
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