Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/19665 )
Change subject: soc/intel/common: Add Intel PCIe common code ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/#/c/19665/3//COMMIT_MSG Commit Message:
Line 8:
Please add a commit message body for an addition of 150 lines of code.
Ok.Done.Sorry to miss that.
https://review.coreboot.org/#/c/19665/3/src/soc/intel/common/block/pcie/Kcon... File src/soc/intel/common/block/pcie/Kconfig:
PS3, Line 8: help
remove this line
Ok.Done.revised under PS#4.
https://review.coreboot.org/#/c/19665/3/src/soc/intel/common/block/pcie/pcie... File src/soc/intel/common/block/pcie/pcie.c:
PS3, Line 42:
if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) {
Ok.Done.Revised under PS#4.
PS3, Line 64: tic void pcie_set_L1_ss_max_latency(device
Where are these Kconfig values? Even if an SoC doesn't want to program this
Ok.Undestood.Revised implementation in PS#4 to be IP centric. Verified the latency values for upcoming platforms are also same.Please review.
PS3, Line 144:
Please use a tabulator.
Done