Change in coreboot[master]: soc/intel/alderlake: Implement WA for DDR5 DIMM modules

[Meera Ravindranath (Code Review)]

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Angel Pons, Patrick Rudolph.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )

Change subject: soc/intel/alderlake: Implement WA for DDR5 DIMM modules
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Patch Set 22:

(2 comments)

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/50996/comment/99e1332b_4468cb30 
PS19, Line 224: spd_addr_array
> This is something that is very mainboard specific. Also, `mem_spd` (https://review.coreboot. […]

Done

https://review.coreboot.org/c/coreboot/+/50996/comment/53d1017c_e0a1484d 
PS19, Line 260: smbus_address_valid = true;
> +2 on splitting the code nicely between mainboard and SoC, i was not very happy to hardcode SMBUS ad […]

Done