Attention is currently required from: Eric Lai, Kapil Porwal, Pranava Y N, Subrata Banik.
Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84236?usp=email )
Change subject: soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways
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Patch Set 3:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/84236/comment/c5320d51_72295a3f?usp... :
PS1, Line 519: add %edx, %eax
I find this a bit suspicous, let's take an example: with `CONFIG_DCACHE_RAM_SIZE` at 0x200000 and […]
Seems better, did you run a debugger to verify that the registers through this logic ?
Now we 3 instructions instead of 3 with an extra label. I had a version like this originally that I discarded as I preferred to not introduce a new label.
I let you decide if you want to proceed with this. I don't see any sinificant improvement with this new version but I am not opposed to it.
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