Change in coreboot[master]: [TESTME] sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in S...

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59934 )

Change subject: [TESTME] sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE
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[TESTME] sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE

Use a read modify write sequence when setting the SPI_USE_SPI100 bit in
the SPI100_ENABLE register. This avoids clearing other bits in the
register which might cause instabilities. Haven't checked the reference
code, but the register descriptions suggested that the register in
Mullins behaves similar to the one in Stoneyridge.

TEST=None

Signed-off-by: Felix Held 
Change-Id: Ifbd960a9509542b28f03326a3066995540260bef
---
M src/southbridge/amd/pi/hudson/early_setup.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59934/1

diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 20597d4..2617985 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -215,7 +215,8 @@
    			(fast << SPI_FAST_SPEED_NEW_SH) |
    			(alt << SPI_ALT_SPEED_NEW_SH) |
    			(tpm << SPI_TPM_SPEED_NEW_SH));
-	write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100);
+	write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100 |
+		read16((void *)(base + SPI100_ENABLE)));
 }

void hudson_disable_4dw_burst(void)