Change in coreboot[master]: soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks

[Michał Żygowski (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63457 )

Change subject: soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks
......................................................................

soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks

ADL-S CPU has maximum 3 PCIe interfaces when the x16 link is bifurcated
into two x8 links. ADL-S PCH has up to 28 PCIe Root Ports, 18 CLKOUT and
CLKREQ signals. ADL-S CPUs do not have Thunderbolt.

Based on the Intel DOC #619501 and #619362.

Signed-off-by: Michał Żygowski 
Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 5 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/63457/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 3608798..27a8fb3 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -212,16 +212,17 @@
    default 10 if SOC_INTEL_ALDERLAKE_PCH_M
    default 12 if SOC_INTEL_ALDERLAKE_PCH_N
    default 12 if SOC_INTEL_ALDERLAKE_PCH_P
+	default 28 if SOC_INTEL_ALDERLAKE_PCH_S

config MAX_CPU_ROOT_PORTS
    int
    default 1 if SOC_INTEL_ALDERLAKE_PCH_M
    default 0 if SOC_INTEL_ALDERLAKE_PCH_N
-	default 3 if SOC_INTEL_ALDERLAKE_PCH_P
+	default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S

config MAX_TBT_ROOT_PORTS
    int
-	default 0 if SOC_INTEL_ALDERLAKE_PCH_N
+	default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S
    default 2 if SOC_INTEL_ALDERLAKE_PCH_M
    default 4 if SOC_INTEL_ALDERLAKE_PCH_P

@@ -234,12 +235,14 @@
    default 6 if SOC_INTEL_ALDERLAKE_PCH_M
    default 5 if SOC_INTEL_ALDERLAKE_PCH_N
    default 7 if SOC_INTEL_ALDERLAKE_PCH_P
+	default 18 if SOC_INTEL_ALDERLAKE_PCH_S

config MAX_PCIE_CLOCK_REQ
    int
    default 6  if SOC_INTEL_ALDERLAKE_PCH_M
    default 5  if SOC_INTEL_ALDERLAKE_PCH_N
    default 10 if SOC_INTEL_ALDERLAKE_PCH_P
+	default 18 if SOC_INTEL_ALDERLAKE_PCH_S

config SMM_TSEG_SIZE
    hex