Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68782 )
Change subject: test]: Add intel CPUID F6x support ......................................................................
test]: Add intel CPUID F6x support
Change-Id: Iaacb856a0064ea57cdcec11a76fab1cd340e2ed8 Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/cpu/intel/Kconfig A src/cpu/intel/model_f6x/Kconfig A src/cpu/intel/model_f6x/Makefile.inc A src/cpu/intel/model_f6x/model_f6x_init.c M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_LGA775/Makefile.inc M src/cpu/intel/speedstep/speedstep.c 7 files changed, 121 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/68782/1
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 43b360b..6fb057e 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -13,6 +13,7 @@ source "src/cpu/intel/model_f2x/Kconfig" source "src/cpu/intel/model_f3x/Kconfig" source "src/cpu/intel/model_f4x/Kconfig" +source "src/cpu/intel/model_f6x/Kconfig" source "src/cpu/intel/haswell/Kconfig" # Sockets/Slots source "src/cpu/intel/slot_1/Kconfig" diff --git a/src/cpu/intel/model_f6x/Kconfig b/src/cpu/intel/model_f6x/Kconfig new file mode 100644 index 0000000..a5b44c9 --- /dev/null +++ b/src/cpu/intel/model_f6x/Kconfig @@ -0,0 +1,5 @@ +config CPU_INTEL_MODEL_F6X + bool + select ARCH_X86 + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f6x/Makefile.inc b/src/cpu/intel/model_f6x/Makefile.inc new file mode 100644 index 0000000..1aaed0a --- /dev/null +++ b/src/cpu/intel/model_f6x/Makefile.inc @@ -0,0 +1,5 @@ +ramstage-y += model_f6x_init.c +subdirs-y += ../smm/gen1 +ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c + +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-06-*) diff --git a/src/cpu/intel/model_f6x/model_f6x_init.c b/src/cpu/intel/model_f6x/model_f6x_init.c new file mode 100644 index 0000000..85ef9bd --- /dev/null +++ b/src/cpu/intel/model_f6x/model_f6x_init.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/msr.h> +#include <device/device.h> + +static void configure_mca(void) +{ + msr_t msr; + int i; + const unsigned int num_banks = mca_get_bank_count(); + + /* Enable all error reporting */ + msr.lo = msr.hi = ~0; + for (i = 0; i < num_banks; i++) + wrmsr(IA32_MC_CTL(i), msr); + + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + mca_clear_status(); +} + + +static void configure_misc(void) +{ + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 3); /* TM1 enable */ + msr.lo |= (1 << 10); /* FERR# multiplexing */ + /* FIXME:SpeedStep Enable - here it hang, but it shouldn't */ + //msr.lo |= (1 << 16); + wrmsr(IA32_MISC_ENABLE, msr); +} + +static void model_f6x_init(struct device *cpu) +{ + + /* Clear out pending MCEs */ + configure_mca(); + + /* Turn on caching if we haven't already */ + enable_cache(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); +}; + +static struct device_operations cpu_dev_ops = { + .init = model_f6x_init, +}; + +static const struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x0f62 }, /* Not tested */ + { X86_VENDOR_INTEL, 0x0f64 }, /* Not tested */ + { X86_VENDOR_INTEL, 0x0f65 }, + { X86_VENDOR_INTEL, 0x0f68 }, /* Not tested */ + { 0, 0 }, +}; + +static const struct cpu_driver model_f6x __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 3c9f262..c6abd10 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -8,6 +8,7 @@ select CPU_INTEL_MODEL_6FX select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X + select CPU_INTEL_MODEL_F6X select CPU_INTEL_MODEL_1067X select MMX select SIPI_VECTOR_IN_ROM diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 9b08be6..259808d 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -1,6 +1,7 @@ subdirs-y += ../model_6fx subdirs-y += ../model_f3x subdirs-y += ../model_f4x +subdirs-y += ../model_f6x subdirs-y += ../model_1067x subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index 9235272..7e8a3de 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -16,23 +16,31 @@ static void speedstep_get_limits(sst_params_t *const params) { msr_t msr; + struct cpuinfo_x86 c;
- const uint16_t cpu_id = (cpuid_eax(1) >> 4) & 0xffff; + get_fms(&c, cpuid_eax(1)); const uint32_t state_mask = /* Penryn supports non integer (i.e. half) ratios. */ - ((cpu_id == 0x1067) ? SPEEDSTEP_RATIO_NONINT : 0) + ((c.x86 == 6 && c.x86_model == 0x17) ? + SPEEDSTEP_RATIO_NONINT : 0) | SPEEDSTEP_RATIO_VALUE_MASK | SPEEDSTEP_VID_MASK;
+ const bool msr_extended_config_supported = c.x86 != 0xf; + const bool msr_platform_info_supported = c.x86 != 0xf; + /* Initialize params to zero. */ memset(params, '\0', sizeof(*params));
+ if (msr_extended_config_supported) { /* Read Super-LFM parameters. */ - if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) {/*supported and - enabled bits */ - msr = rdmsr(MSR_FSB_CLOCK_VCC); - params->slfm = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); - params->slfm.dynfsb = 1; - params->slfm.is_slfm = 1; + /* If (supported and enabled bits) */ + if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) { + msr = rdmsr(MSR_FSB_CLOCK_VCC); + params->slfm = + SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); + params->slfm.dynfsb = 1; + params->slfm.is_slfm = 1; + } }
/* Read normal minimum parameters. */ @@ -45,7 +53,7 @@ when using turbo mode. */ msr = rdmsr(IA32_PLATFORM_ID); params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); - if (cpu_id == 0x006e) { + if ((c.x86 == 6 && c.x86_model == 0xe) || c.x86 == 0xf) { /* Looks like Yonah CPUs don't have the frequency ratio in IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading should be reliable as those CPUs don't have turbo mode. */ @@ -54,41 +62,38 @@ >> SPEEDSTEP_RATIO_SHIFT; }
- /* Read turbo parameters. */ - msr = rdmsr(MSR_FSB_CLOCK_VCC); - if ((msr.hi & (1 << (63 - 32))) && - /* supported and */ - !(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) { - /* not disabled */ - params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); - params->turbo.is_turbo = 1; + if (msr_platform_info_supported) { + /* Read turbo parameters. */ + msr = rdmsr(MSR_FSB_CLOCK_VCC); + if ((msr.hi & (1 << (63 - 32))) && + /* supported and */ + !(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) { + /* not disabled */ + params->turbo = + SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); + params->turbo.is_turbo = 1; + } }
/* Set power limits by processor type. */ /* Defined values match the normal voltage versions only. But they are only a hint for OSPM, so this should not hurt much. */ - switch (cpu_id) { - case 0x006e: + if (c.x86 == 6 && c.x86_model == 0xe) { /* Yonah */ params->min.power = SPEEDSTEP_MIN_POWER_YONAH; params->max.power = SPEEDSTEP_MAX_POWER_YONAH; - break; - case 0x1067: + } else if (c.x86 == 6 && c.x86_model == 0x17) { /* Penryn */ params->slfm.power = SPEEDSTEP_SLFM_POWER_PENRYN; params->min.power = SPEEDSTEP_MIN_POWER_PENRYN; params->max.power = SPEEDSTEP_MAX_POWER_PENRYN; params->turbo.power = SPEEDSTEP_MAX_POWER_PENRYN; - break; - case 0x006f: - /* Merom */ - default: + } else { /* Use Merom values by default (as before). */ params->slfm.power = SPEEDSTEP_SLFM_POWER_MEROM; params->min.power = SPEEDSTEP_MIN_POWER_MEROM; params->max.power = SPEEDSTEP_MAX_POWER_MEROM; params->turbo.power = SPEEDSTEP_MAX_POWER_MEROM; - break; } }
-
Elyes Haouas (Code Review)