[S] Change in coreboot[master]: soc/intel/alderlake: Add/Remove LTR disqualification

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68251 )

Change subject: soc/intel/alderlake: Add/Remove LTR disqualification
......................................................................

soc/intel/alderlake: Add/Remove LTR disqualification

a) Add LTR disqualification in D3 to ensure PMC ignores LTR
from UFS IP as it is infinite.
b) Remove LTR disqualification in _PS0 to ensure PMC stops
ignoring LTR from UFS IP during D3 exit.

Signed-off-by: Meera Ravindranath 
Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c
---
M src/soc/intel/alderlake/acpi/ufs.asl
1 file changed, 31 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/68251/1

diff --git a/src/soc/intel/alderlake/acpi/ufs.asl b/src/soc/intel/alderlake/acpi/ufs.asl
index d6774f8..7cbcc17 100644
--- a/src/soc/intel/alderlake/acpi/ufs.asl
+++ b/src/soc/intel/alderlake/acpi/ufs.asl
@@ -69,18 +69,34 @@
    		PGEN, 1	/* [BIT2] PGE - PG Enable */
    	}

+		/* PWRM register definitions */
+		OperationRegion(PWMR, SystemMemory, 0xFE000000, 0x1E30)
+		Field(PWMR, DWordAcc, NoLock, Preserve)
+		{
+			Offset(R_PMC_PWRM_LTR_IGN),
+			, 18,
+			LTRU,  1,         // Bit 18, IGN_UFSX2
+		}
+
+		Method (ULTR, 1, Serialized) {
+			Store(Arg0, LTRU)
+		}
+
    	Method (_PS0, 0, Serialized)
    	{
    		Store(0, PGEN) /* Disable PG */

And(PSTA, 0xFFFFFFFC, PSTA) /* Set BIT[1:0] = 00b - Power State D0 */

+			ULTR (0)
+
    		/* Disable OCP Timer in SCS UFS IOSF Bridge */
    		OCPD ()
    	}

Method (_PS3, 0, Serialized)
    	{
+			ULTR (1)

Store(1, PGEN)	/* Enable PG */
    	}