[M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels

[Subrata Banik (Code Review)]

Attention is currently required from: Christian Walter, Dinesh Gehlot, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Paul Menzel, Piotr Król, Sean Rhodes, Tim Crawford.

Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email )

Change subject: soc/intel/alderlake: Add function to force disable memory channels
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Patch Set 6:

(1 comment)

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/85529/comment/86820161_8b615a77?usp... :
PS1, Line 252: 	if (ch_disable_mask == 0) {
> I think this CL is to provide an additional option to disable memory channels. Originally we could only use half_populated variable to turn off half of channels.
> However, even with this CL to disable channels, users need still follow Intel PDG for proper usage.
> We can skip checking these conditions because if config incorrect combinations, the FSP will return a "Memory initialization has failed" error. It's easy to identify.

Partners can't readily understand the reason for the failure by looking at just the coreboot log. The log only says "FSP memoryinit error," and one would need to build FSP in debug mode to get more data. This data is often not readily available as part of CPFE AP FW build. I would still like to keep the minimal configuration, like not disabling MC0CH0. If such a design is seen, we should trigger an error before even calling into FSP..