Change in coreboot[master]: [WIP] soc/amd/sabrina/i2c: only call fch_i2c_pad_init for bus 3

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61570 )

Change subject: [WIP] soc/amd/sabrina/i2c: only call fch_i2c_pad_init for bus 3
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[WIP] soc/amd/sabrina/i2c: only call fch_i2c_pad_init for bus 3

I2C bus 0..2 on Sabrina uses a different pad type.

Signed-off-by: Felix Held 
Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375
---
M src/soc/amd/sabrina/i2c.c
1 file changed, 5 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/61570/1

diff --git a/src/soc/amd/sabrina/i2c.c b/src/soc/amd/sabrina/i2c.c
index 076a0f2..028f0a8 100644
--- a/src/soc/amd/sabrina/i2c.c
+++ b/src/soc/amd/sabrina/i2c.c
@@ -42,7 +42,11 @@
    if (bus >= ARRAY_SIZE(config->i2c_pad))
    	return;

-	fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
+	if (bus <= 2) {
+		//TODO
+	} else {
+		fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
+	}
 }

const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)