Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Lean Sheng Tan, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56633 )
Change subject: soc/intel/elkhartlake: Add PSE TSN support ......................................................................
Patch Set 25:
(9 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56633/comment/49702fdf_699855d0 PS25, Line 13: PSSE PSE?
File src/soc/intel/elkhartlake/chip.h:
https://review.coreboot.org/c/coreboot/+/56633/comment/4e2fa44b_cf3c634d PS25, Line 26: Extra TAB not needed.
https://review.coreboot.org/c/coreboot/+/56633/comment/8f4b6cc3_632d7f33 PS25, Line 476: 2 Use MAX_PSE_TSN_PORTS here instead?
https://review.coreboot.org/c/coreboot/+/56633/comment/9e0bb5ea_548c827c PS25, Line 479: 2 MAX_PSE_TSN_PORTS as well?
https://review.coreboot.org/c/coreboot/+/56633/comment/597a39a4_160b6549 PS25, Line 482: 2 And here MAX_PSE_TSN_PORTS, too?
https://review.coreboot.org/c/coreboot/+/56633/comment/71f427ab_758e2c23 PS25, Line 484: 2 Same here?
https://review.coreboot.org/c/coreboot/+/56633/comment/500ae282_04cb1174 PS25, Line 510: 2 Would MAX_PSE_TSN_PORTS make sense here?
File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/56633/comment/8775f9eb_40b9b12a PS25, Line 89: configs setup config values
https://review.coreboot.org/c/coreboot/+/56633/comment/192b9b80_f529c2eb PS25, Line 89: 'in' or 'from'
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Werner Zeh (Code Review)