Change in coreboot[master]: mb/asrock/g41c-gs: Add IO decode range for SIO HWMON

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21464

Change subject: mb/asrock/g41c-gs: Add IO decode range for SIO HWMON
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mb/asrock/g41c-gs: Add IO decode range for SIO HWMON

Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736
Signed-off-by: Arthur Heymans 
---
M src/mainboard/asrock/g41c-gs/romstage.c
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21464/1

diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index 73fd935..ea0d995 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -75,6 +75,7 @@
    /* Decode range */
    pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
    		| KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0281);
 }

void mainboard_romstage_entry(unsigned long bist)