Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41068 )
Change subject: soc/amd/common/block/lpc: Use standard pci_dev_ops_pci ......................................................................
soc/amd/common/block/lpc: Use standard pci_dev_ops_pci
AMD common block LPC driver does not really need a custom ops_pci structure. This change drops the lops_pci and instead set .ops_pci to the default pci_dev_ops_pci.
BUG=b:154445472
Change-Id: Ia06eed04097739c3e21dc13e056a2120ff5eb382 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 1 insertion(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/41068/1
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 0c98fcb..54befef 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -306,10 +306,6 @@ lpc_enable_childrens_resources(dev); }
-static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, @@ -318,7 +314,7 @@ .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .scan_bus = scan_static_bus, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, };
static const unsigned short pci_device_ids[] = {
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41068 )
Change subject: soc/amd/common/block/lpc: Use standard pci_dev_ops_pci ......................................................................
Patch Set 1: Code-Review+2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41068 )
Change subject: soc/amd/common/block/lpc: Use standard pci_dev_ops_pci ......................................................................
Patch Set 1: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41068 )
Change subject: soc/amd/common/block/lpc: Use standard pci_dev_ops_pci ......................................................................
soc/amd/common/block/lpc: Use standard pci_dev_ops_pci
AMD common block LPC driver does not really need a custom ops_pci structure. This change drops the lops_pci and instead set .ops_pci to the default pci_dev_ops_pci.
BUG=b:154445472
Change-Id: Ia06eed04097739c3e21dc13e056a2120ff5eb382 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41068 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 1 insertion(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 0c98fcb..54befef 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -306,10 +306,6 @@ lpc_enable_childrens_resources(dev); }
-static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, @@ -318,7 +314,7 @@ .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .scan_bus = scan_static_bus, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, };
static const unsigned short pci_device_ids[] = {
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41068 )
Change subject: soc/amd/common/block/lpc: Use standard pci_dev_ops_pci ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3239 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3238 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3237 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3236
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Felix Held (Code Review)
-
Furquan Shaikh (Code Review)
-
Raul Rangel (Code Review)