Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76044?usp=email )
Change subject: include/intel/post_code.h: Change post code prefix to POSTCODE ......................................................................
include/intel/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name.
The files was changed by running the following bash script from the top level directory.
filedir=src/include/cpu/intel/post_codes.h sed -i'' '1,${s/#define POST_/#define POSTCODE_/g;}' $filedir myArray=`grep -e "^#define POSTCODE_" $filedir | grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2` for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g" done
Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: lilacious yuchenhe126@gmail.com --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/include/cpu/intel/post_codes.h M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/include/intelblocks/post_codes.h 9 files changed, 71 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/76044/1
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 316b703..9c60308 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -29,7 +29,7 @@ bt $12, %eax jc wait_for_sipi
- post_code(POST_SOC_CLEAR_FIXED_MTRRS) + post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS)
/* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list, %ebx @@ -59,7 +59,7 @@ dec %ebx jnz clear_var_mtrr
- post_code(POST_SOC_SET_DEF_MTRR_TYPE) + post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr @@ -84,7 +84,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr
- post_code(POST_SOC_SET_MTRR_BASE) + post_code(POSTCODE_SOC_SET_MTRR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -92,7 +92,7 @@ xorl %edx, %edx wrmsr
- post_code(POST_SOC_SET_MTRR_MASK) + post_code(POSTCODE_SOC_SET_MTRR_MASK) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -100,7 +100,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(POST_SOC_ENABLE_MTRRS) + post_code(POSTCODE_SOC_ENABLE_MTRRS)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -128,7 +128,7 @@ shr $2, %ecx rep stosl
- post_code(POST_SOC_DISABLE_CACHE) + post_code(POSTCODE_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -147,7 +147,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(POST_SOC_ENABLE_CACHE) + post_code(POSTCODE_SOC_ENABLE_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -181,7 +181,7 @@ #endif
before_c_entry: - post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 187b1ca..18ac070 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -34,14 +34,14 @@ bt $12, %eax jc wait_for_sipi
- post_code(POST_SOC_SET_DEF_MTRR_TYPE) + post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE) /* Clean-up MTRR_DEF_TYPE_MSR. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr
- post_code(POST_SOC_CLEAR_FIXED_MTRRS) + post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list, %ebx xor %eax, %eax @@ -88,7 +88,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr
- post_code(POST_SOC_SET_MTRR_BASE) + post_code(POSTCODE_SOC_SET_MTRR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl car_mtrr_start, %eax @@ -96,7 +96,7 @@ xorl %edx, %edx wrmsr
- post_code(POST_SOC_SET_MTRR_MASK) + post_code(POSTCODE_SOC_SET_MTRR_MASK) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -117,7 +117,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(POST_SOC_ENABLE_MTRRS) + post_code(POSTCODE_SOC_ENABLE_MTRRS)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -188,7 +188,7 @@ orl $3, %eax wrmsr
- post_code(POST_SOC_DISABLE_CACHE) + post_code(POSTCODE_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -199,7 +199,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(POST_SOC_ENABLE_CACHE) + post_code(POSTCODE_SOC_ENABLE_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -234,7 +234,7 @@ #endif
before_c_entry: - post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 56370f8..9e37b46 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -13,14 +13,14 @@ chipset_teardown_car: pop %esp
- post_code(POST_POSTCAR_DISABLE_CACHE) + post_code(POSTCODE_POSTCAR_DISABLE_CACHE)
/* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0
- post_code(POST_POSTCAR_DISABLE_DEF_MTRR) + post_code(POSTCODE_POSTCAR_DISABLE_DEF_MTRR)
/* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -36,7 +36,7 @@ andl $~1, %eax wrmsr
- post_code(POST_POSTCAR_TEARDOWN_DONE) + post_code(POSTCODE_POSTCAR_TEARDOWN_DONE)
/* Return to caller. */ jmp *%esp diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 1431d32..779dbcc 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -42,7 +42,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(POST_SOC_SET_DEF_MTRR_TYPE) + post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
/* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -50,7 +50,7 @@ andl $(~0x00000cff), %eax wrmsr
- post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) + post_code(POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS)
/* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax @@ -68,7 +68,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr
- post_code(POST_SOC_SET_CAR_BASE) + post_code(POSTCODE_SOC_SET_CAR_BASE)
/* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -84,7 +84,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(POST_SOC_ENABLE_MTRRS) + post_code(POSTCODE_SOC_ENABLE_MTRRS)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -92,7 +92,7 @@ orl $MTRR_DEF_TYPE_EN, %eax wrmsr
- post_code(POST_SOC_ENABLE_CACHE) + post_code(POSTCODE_SOC_ENABLE_CACHE)
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax @@ -114,7 +114,7 @@ xorl %eax, %eax rep stosl
- post_code(POST_SOC_DISABLE_CACHE) + post_code(POSTCODE_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -133,7 +133,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(POST_SOC_FILL_CACHE) + post_code(POSTCODE_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -156,7 +156,7 @@ pushl %eax /* tsc[31:0] */
before_c_entry: - post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 0362d10..9f514ef 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -54,7 +54,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(POST_SOC_SET_DEF_MTRR_TYPE) + post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
/* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -62,7 +62,7 @@ andl $(~0x00000cff), %eax wrmsr
- post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) + post_code(POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS)
/* Determine CPU_ADDR_BITS and load PHYSMASK high * word to %edx. @@ -106,7 +106,7 @@
bsp_init:
- post_code(POST_SOC_BSP_INIT) + post_code(POSTCODE_SOC_BSP_INIT)
/* Send INIT IPI to all excluding ourself. */ movl LAPIC(ICR), %edi @@ -120,7 +120,7 @@ andl $LAPIC_ICR_BUSY, %ecx jnz 1b
- post_code(POST_SOC_COUNT_CORES) + post_code(POSTCODE_SOC_COUNT_CORES)
movl $1, %eax cpuid @@ -155,7 +155,7 @@
hyper_threading_cpu:
- post_code(POST_SOC_CPU_HYPER_THREADING) + post_code(POSTCODE_SOC_CPU_HYPER_THREADING)
/* Send Start IPI to all excluding ourself. */ movl LAPIC(ICR), %edi @@ -170,7 +170,7 @@ andl $LAPIC_ICR_BUSY, %ecx jnz 1b
- post_code(POST_SOC_CPU_SIBLING_DELAY) + post_code(POSTCODE_SOC_CPU_SIBLING_DELAY)
/* Wait for sibling CPU to start. */ 1: movl $(MTRR_PHYS_BASE(0)), %ecx @@ -186,14 +186,14 @@
ap_init: - post_code(POST_SOC_CPU_AP_INIT) + post_code(POSTCODE_SOC_CPU_AP_INIT)
/* Do not disable cache (so BSP can enable it). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0
- post_code(POST_SOC_SET_MTRR_BASE) + post_code(POSTCODE_SOC_SET_MTRR_BASE)
/* MTRR registers are shared between HT siblings. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -201,7 +201,7 @@ xorl %edx, %edx wrmsr
- post_code(POST_SOC_AP_HALT) + post_code(POSTCODE_SOC_AP_HALT)
ap_halt: cli @@ -212,7 +212,7 @@
sipi_complete:
- post_code(POST_SOC_SET_CAR_BASE) + post_code(POSTCODE_SOC_SET_CAR_BASE)
/* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -228,7 +228,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(POST_SOC_ENABLE_MTRRS) + post_code(POSTCODE_SOC_ENABLE_MTRRS)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -271,7 +271,7 @@ wrmsr no_msr_11e:
- post_code(POST_SOC_ENABLE_CACHE) + post_code(POSTCODE_SOC_ENABLE_CACHE)
/* Cache the whole rom to fetch microcode updates */ movl $MTRR_PHYS_BASE(1), %ecx @@ -298,7 +298,7 @@ jmp update_bsp_microcode end_microcode_update: #endif - post_code(POST_SOC_DISABLE_CACHE) + post_code(POSTCODE_SOC_DISABLE_CACHE) /* Disable caching to change MTRR's. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -338,7 +338,7 @@ wrmsr
fill_cache: - post_code(POST_SOC_FILL_CACHE) + post_code(POSTCODE_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -381,7 +381,7 @@ #endif
before_c_entry: - post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 1684407..05f7751 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -11,14 +11,14 @@ chipset_teardown_car: pop %esp
- post_code(POST_POSTCAR_DISABLE_CACHE) + post_code(POSTCODE_POSTCAR_DISABLE_CACHE)
/* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0
- post_code(POST_POSTCAR_DISABLE_DEF_MTRR) + post_code(POSTCODE_POSTCAR_DISABLE_DEF_MTRR)
/* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -26,7 +26,7 @@ andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr
- post_code(POST_POSTCAR_TEARDOWN_DONE) + post_code(POSTCODE_POSTCAR_TEARDOWN_DONE)
/* Return to caller. */ jmp *%esp diff --git a/src/include/cpu/intel/post_codes.h b/src/include/cpu/intel/post_codes.h index 6c1ca79..40738b1 100644 --- a/src/include/cpu/intel/post_codes.h +++ b/src/include/cpu/intel/post_codes.h @@ -3,26 +3,26 @@ #ifndef CPU_INTEL_CAR_POST_CODES_H #define CPU_INTEL_CAR_POST_CODES_H
-#define POST_SOC_SET_DEF_MTRR_TYPE 0x21 -#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate -#define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22 -#define POST_SOC_BSP_INIT 0x23 -#define POST_SOC_COUNT_CORES 0x24 -#define POST_SOC_CPU_HYPER_THREADING 0x25 -#define POST_SOC_CPU_SIBLING_DELAY 0x26 -#define POST_SOC_CPU_AP_INIT 0x27 -#define POST_SOC_SET_MTRR_BASE 0x28 -#define POST_SOC_SET_MTRR_MASK 0x29 // Intentional Duplicate -#define POST_SOC_AP_HALT 0x29 -#define POST_SOC_SET_CAR_BASE 0x2a -#define POST_SOC_ENABLE_MTRRS 0x2b -#define POST_SOC_ENABLE_CACHE 0x2c -#define POST_SOC_DISABLE_CACHE 0x2d -#define POST_SOC_FILL_CACHE 0x2e -#define POST_BOOTBLOCK_BEFORE_C_ENTRY 0x2f +#define POSTCODE_SOC_SET_DEF_MTRR_TYPE 0x21 +#define POSTCODE_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate +#define POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS 0x22 +#define POSTCODE_SOC_BSP_INIT 0x23 +#define POSTCODE_SOC_COUNT_CORES 0x24 +#define POSTCODE_SOC_CPU_HYPER_THREADING 0x25 +#define POSTCODE_SOC_CPU_SIBLING_DELAY 0x26 +#define POSTCODE_SOC_CPU_AP_INIT 0x27 +#define POSTCODE_SOC_SET_MTRR_BASE 0x28 +#define POSTCODE_SOC_SET_MTRR_MASK 0x29 // Intentional Duplicate +#define POSTCODE_SOC_AP_HALT 0x29 +#define POSTCODE_SOC_SET_CAR_BASE 0x2a +#define POSTCODE_SOC_ENABLE_MTRRS 0x2b +#define POSTCODE_SOC_ENABLE_CACHE 0x2c +#define POSTCODE_SOC_DISABLE_CACHE 0x2d +#define POSTCODE_SOC_FILL_CACHE 0x2e +#define POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY 0x2f
-#define POST_POSTCAR_DISABLE_CACHE 0x30 -#define POST_POSTCAR_DISABLE_DEF_MTRR 0x31 -#define POST_POSTCAR_TEARDOWN_DONE 0x32 +#define POSTCODE_POSTCAR_DISABLE_CACHE 0x30 +#define POSTCODE_POSTCAR_DISABLE_DEF_MTRR 0x31 +#define POSTCODE_POSTCAR_TEARDOWN_DONE 0x32
#endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5f6b6de..1b393d41 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -112,7 +112,7 @@ cmp $fixed_mtrr_list_end, %ebx jl clear_fixed_mtrr
- post_code(POST_SOC_CLEAR_FIXED_MTRRS) + post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS)
/* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -333,7 +333,7 @@
clear_car
- post_code(POST_SOC_DISABLE_CACHE_EVICT) + post_code(POSTCODE_SOC_DISABLE_CACHE_EVICT)
/* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx @@ -422,7 +422,7 @@
clear_car
- post_code(POST_SOC_DISABLE_CACHE_EVICT) + post_code(POSTCODE_SOC_DISABLE_CACHE_EVICT)
/* Cache is populated. Use mask 1 that will block evicts */ mov $IA32_PQR_ASSOC, %ecx @@ -634,7 +634,7 @@ #endif wrmsr
- post_code(POST_SOC_DISABLE_CACHE_EVICT) + post_code(POSTCODE_SOC_DISABLE_CACHE_EVICT) /* * Enable No-Eviction Mode Run State by setting * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. diff --git a/src/soc/intel/common/block/include/intelblocks/post_codes.h b/src/soc/intel/common/block/include/intelblocks/post_codes.h index 7c78ef8..b04b1ac 100644 --- a/src/soc/intel/common/block/include/intelblocks/post_codes.h +++ b/src/soc/intel/common/block/include/intelblocks/post_codes.h @@ -6,12 +6,12 @@ /* common/block/cpu/car/cache_as_ram.s */ #define POST_BOOTBLOCK_PRE_C_ENTRY 0x20 #define POST_SOC_NO_RESET 0x21 -#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 +#define POSTCODE_SOC_CLEAR_FIXED_MTRRS 0x22 #define POST_SOC_CLEAR_VAR_MTRRS 0x23 #define POST_SOC_SET_UP_CAR_MTRRS 0x24 #define POST_SOC_BOOTGUARD_SETUP 0x25 #define POST_SOC_CLEARING_CAR 0x26 -#define POST_SOC_DISABLE_CACHE_EVICT 0x27 +#define POSTCODE_SOC_DISABLE_CACHE_EVICT 0x27 #define POST_SOC_CAR_NEM_ENHANCED 0x28 #define POST_SOC_CAR_INIT_DONE 0x29 #define POST_SOC_BEFORE_CARSTAGE 0x2a