Patch set updated for coreboot: 6897c69 Re-factor 'to_flash_offset()' into 'spi_flash.h'
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5834
-gerrit
commit 6897c691098b11785c6d3394a3ff3463e4eacda2 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Sat May 24 04:09:50 2014 +1000
Re-factor 'to_flash_offset()' into 'spi_flash.h'
Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by Clang complaining that the function 'to_flash_offset' is unused.
Change-Id: I129cf8349e9ee2ebd4a4d0f69a6d830bdbc4ebf0 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/drivers/intel/fsp/Kconfig | 14 -------------- src/drivers/intel/fsp/fastboot_cache.c | 13 ++----------- src/include/spi_flash.h | 7 +++++++ src/northbridge/intel/haswell/mrccache.c | 8 ++------ src/northbridge/intel/sandybridge/mrccache.c | 8 ++------ src/soc/intel/baytrail/nvm.c | 10 ++-------- src/soc/intel/fsp_baytrail/nvm.c | 13 ++----------- 7 files changed, 17 insertions(+), 56 deletions(-)
diff --git a/src/drivers/intel/fsp/Kconfig b/src/drivers/intel/fsp/Kconfig index 5e44046..7774831 100644 --- a/src/drivers/intel/fsp/Kconfig +++ b/src/drivers/intel/fsp/Kconfig @@ -104,20 +104,6 @@ config MRC_CACHE_LOC and nothing else should be included in that sector, or IT WILL BE ERASED.
-config VIRTUAL_ROM_SIZE - hex "Virtual ROM Size" - default ROM_SIZE - depends on ENABLE_MRC_CACHE - help - This is used to calculate the offset of the MRC data cache in NV - Storage for fast boot. If in doubt, leave this set to the default - which sets the virtual size equal to the ROM size. - - Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are - loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When - the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM - size is 16 MB. - endif #HAVE_FSP_BIN
config CACHE_ROM_SIZE_OVERRIDE diff --git a/src/drivers/intel/fsp/fastboot_cache.c b/src/drivers/intel/fsp/fastboot_cache.c index b9a6e33..2ceb5db 100644 --- a/src/drivers/intel/fsp/fastboot_cache.c +++ b/src/drivers/intel/fsp/fastboot_cache.c @@ -31,15 +31,6 @@ #include <lib.h> // hexdump #include "fsp_util.h"
-#ifndef CONFIG_VIRTUAL_ROM_SIZE -#error "CONFIG_VIRTUAL_ROM_SIZE must be set." -#endif - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -205,7 +196,7 @@ void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base);
- flash->erase(flash, to_flash_offset(cache_base), cache_size); + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size);
/* we will start at the beginning again */ cache = cache_base; @@ -213,7 +204,7 @@ void update_mrc_cache(void *unused) /* 4. write mrc data with flash->write() */ printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(cache), + flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); }
diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index fe48d3b..dfd31b8 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -87,4 +87,11 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, return flash->erase(flash, offset, len); }
+#if !defined(__PRE_RAM__) +/* convert a pointer to flash area into the offset inside the flash */ +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { + return ((u32)p + flash->size); +} +#endif /* !defined(__PRE_RAM__) */ + #endif /* _SPI_FLASH_H_ */ diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 88dbf7f..a694af8 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif
-/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -124,6 +119,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ + #if !defined(__PRE_RAM__) /* find the first empty block in the MRC cache area. * If there's none, return NULL. @@ -228,7 +224,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */
struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 5d7c49b..699a35a 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif
-/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -123,6 +118,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ + #if !defined(__PRE_RAM__) /* find the first empty block in the MRC cache area. * If there's none, return NULL. @@ -227,7 +223,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */
struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/soc/intel/baytrail/nvm.c b/src/soc/intel/baytrail/nvm.c index 843bc5a..f2d58ba 100644 --- a/src/soc/intel/baytrail/nvm.c +++ b/src/soc/intel/baytrail/nvm.c @@ -46,12 +46,6 @@ static int nvm_init(void) return 0; }
-/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -70,7 +64,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + flash->erase(flash, to_flash_offset(flash, start), size); return 0; }
@@ -79,6 +73,6 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + flash->write(flash, to_flash_offset(flash, start), size, data); return 0; } diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c index dab87ae..8ddf563 100644 --- a/src/soc/intel/fsp_baytrail/nvm.c +++ b/src/soc/intel/fsp_baytrail/nvm.c @@ -47,15 +47,6 @@ static int nvm_init(void) return 0; }
-/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ -#ifndef CONFIG_ROM_SIZE -#error CONFIG_ROM_SIZE must be set. -#endif - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -74,7 +65,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + flash->erase(flash, to_flash_offset(flash, start), size); return 0; }
@@ -83,6 +74,6 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + flash->write(flash, to_flash_offset(flash, start), size, data); return 0; }
-
Edward O'Callaghan