Attention is currently required from: Cliff Huang, Sridhar Siricilla, Bernardo Perez Priego, Patrick Rudolph. Hello build bot (Jenkins), Cliff Huang, Tim Wawrzynczak, Sridhar Siricilla, Bernardo Perez Priego, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58125
to look at the new patch set (#18).
Change subject: soc/intel/alderlake: Enable support for CSE stitching ......................................................................
soc/intel/alderlake: Enable support for CSE stitching
This change enables support for stitching of BP1 and BP2 partitions for CSE. This currently mimics what Intel FIT tool does w.r.t. adding different components to the different partitions.
BP1: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP. * Decomposed components from CSE FPT file: RBEP, MFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC.
BP2: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP, ISHP. * Decomposed components from CSE FPT file: RBEP, FTPR, NFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC, IUNP.
BUG=b:189177580,b:189177538
Change-Id: I2b14405aab2a4919431d9c16bc7ff2eb1abf1f6b Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc 2 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/58125/18