[S] Change in coreboot[main]: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet

[Maximilian Brune (Code Review)]

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84613?usp=email )

Change subject: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet
......................................................................

soc/amd/.../amd_pci_int_defs.h: Update according to datasheet

HPET and MISC2/3 and registers are used interchangeably in the
datasheets. Add an alias to emphasis that they refer to the same.

source:
PPR #57396 Rev 3.10 Table "ValidValuesTable: PCI interrupt index list"
PPR #57254 Rev 1.59 Table "ValidValuesTable: PCI interrupt index list"
PPR #57396 Rev 3.10 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map
PPR #57254 Rev 1.59 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map

Change-Id: Ic7b72040f8c4ce39b8f33699e56c0d99d102725f
Signed-off-by: Maximilian Brune 
---
M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
M src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h
2 files changed, 8 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/84613/1

diff --git a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
index 3a9d9b5..0398315 100644
--- a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
+++ b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
@@ -21,8 +21,10 @@
 #define PIRQ_H		0x07	/* INT H */
 #define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings */
 #define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
-#define PIRQ_HPET_L	0x0a	/* HPET TMR{0..2}_CONF_CAP_H[0:7] */
-#define PIRQ_HPET_H	0x0b	/* HPET TMR{0..2}_CONF_CAP_H[15:8] */
+#define PIRQ_MISC1	0x0a	/* Miscellaneous1 IRQ Settings */
+#define PIRQ_MISC2	0x0b	/* Miscellaneous2 IRQ Settings */
+#define PIRQ_HPET_L PIRQ_MISC1	/* HPET TMR{0..2}_CONF_CAP_L[0:7] */
+#define PIRQ_HPET_H PIRQ_MISC2	/* HPET TMR{0..2}_CONF_CAP_H[15:8] */
 #define PIRQ_SIRQA	0x0c	/* Serial IRQ INTA */
 #define PIRQ_SIRQB	0x0d	/* Serial IRQ INTB */
 #define PIRQ_SIRQC	0x0e	/* Serial IRQ INTC */
diff --git a/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h b/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h
index 52cca1a..74bb454 100644
--- a/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h
+++ b/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h
@@ -19,8 +19,10 @@
 #define PIRQ_H		0x07	/* INT H */
 #define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings */
 #define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
-#define PIRQ_HPET_L	0x0a	/* HPET TMR{0..2}_CONF_CAP_H[0:7] */
-#define PIRQ_HPET_H	0x0b	/* HPET TMR{0..2}_CONF_CAP_H[15:8] */
+#define PIRQ_MISC1	0x0a	/* Miscellaneous1 IRQ Settings */
+#define PIRQ_MISC2	0x0b	/* Miscellaneous2 IRQ Settings */
+#define PIRQ_HPET_L PIRQ_MISC1	/* HPET TMR{0..2}_CONF_CAP_L[0:7] */
+#define PIRQ_HPET_H PIRQ_MISC2	/* HPET TMR{0..2}_CONF_CAP_H[15:8] */
 #define PIRQ_SIRQA	0x0c	/* Serial IRQ INTA */
 #define PIRQ_SIRQB	0x0d	/* Serial IRQ INTB */
 #define PIRQ_SIRQC	0x0e	/* Serial IRQ INTC */