Change in coreboot[master]: mb/intel/shadowmountain: Add the ASL code

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49733 )

Change subject: mb/intel/shadowmountain: Add the ASL code
......................................................................

mb/intel/shadowmountain: Add the ASL code

This patch includes the ASL code for shadowmountain board.

BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the ASL entries.

Signed-off-by: V Sowmya 
Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e
---
M src/mainboard/intel/shadowmountain/dsdt.asl
1 file changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/49733/1

diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl
index 10d08e2..4e9f8f0 100644
--- a/src/mainboard/intel/shadowmountain/dsdt.asl
+++ b/src/mainboard/intel/shadowmountain/dsdt.asl
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

#include <acpi/acpi.h>
+#include <baseboard/ec.h>
+#include <baseboard/gpio.h>

DefinitionBlock(
    "dsdt.aml",
@@ -11,4 +13,35 @@
    0x20110725	// OEM revision
 )
 {
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	// CPU
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+			#include <soc/intel/alderlake/acpi/southbridge.asl>
+			#include <soc/intel/alderlake/acpi/tcss.asl>
+		}
+	}
+
+	// Chrome OS specific
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	// Chrome OS Embedded Controller
+	Scope (_SB.PCI0.LPCB)
+	{
+		// ACPI code for EC SuperIO functions
+		#include <ec/google/chromeec/acpi/superio.asl>
+		// ACPI code for EC functions
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
 }