Change in coreboot[master]: nb/intel/pineview/memmap.c: Use `postcar_enable_tseg_cache`

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45917 )

Change subject: nb/intel/pineview/memmap.c: Use `postcar_enable_tseg_cache`
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nb/intel/pineview/memmap.c: Use `postcar_enable_tseg_cache`

Also adjust the comments accordingly.

Change-Id: I4cf11f205182fb18e92227e4d4dcdc8368a5598b
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/pineview/memmap.c
1 file changed, 4 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45917/1

diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index bebe3a5..d26ae01 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -126,12 +126,10 @@
 {
    uintptr_t top_of_ram;

-	/*
-	 * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both
-	 * CBMEM and the TSEG region.
-	 */
+	/* Cache 8 MiB region below the top of RAM to cover CBMEM */
    top_of_ram = (uintptr_t)cbmem_top();
    postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK);
-	postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(),
-			       MTRR_TYPE_WRBACK);
+
+	/* Cache the TSEG region */
+	postcar_enable_tseg_cache(pcf);
 }

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45917 )

Change subject: nb/intel/pineview/memmap.c: Use `postcar_enable_tseg_cache`
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Patch Set 2: Code-Review-2

On hold until the purpose of caching what is marked as TSEG is clear. This might have to do with the stage cache.

[Angel Pons (Code Review)]

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45917 )

Change subject: nb/intel/pineview/memmap.c: Use `postcar_enable_tseg_cache`
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Abandoned